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2010 – 2019
- 2015
[c7]Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao:
Case study of process and design performance debugging with Digital Speed Sensor. VLSI-DAT 2015: 1-4- 2014
- [j12]Chao-Wen Tzeng, Shi-Yu Huang, Pei-Ying Chao:
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 621-630 (2014) - 2013
- [j11]Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou:
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 908-917 (2013) - [j10]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
:
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 329-341 (2013) - [j9]Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang:
Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2240-2249 (2013) - [j8]Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng:
Cell-Based Process Resilient Multiphase Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2348-2352 (2013) - [c6]Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu:
Case study of yield learning through in-house flow of volume diagnosis. VLSI-DAT 2013: 1-4 - 2012
- [c5]Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng:
Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property. VLSI-DAT 2012: 1-4 - 2011
- [c4]Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao:
A fully cell-based design for timing measurement of memory. ITC 2011: 1-10 - 2010
- [j7]Chao-Wen Tzeng, Shi-Yu Huang:
Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 834-839 (2010) - [c3]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang:
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT 2010: 340-348
2000 – 2009
- 2009
- [j6]Chao-Wen Tzeng, Han-Chia Cheng, Shi-Yu Huang:
Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 764-769 (2009) - [j5]Chao-Wen Tzeng, Shi-Yu Huang:
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1756-1766 (2009) - [c2]Chao-Wen Tzeng, Shi-Yu Huang:
QC-Fill: An X-Fill method for quick-and-cool scan test. DATE 2009: 1142-1147 - 2008
- [j4]Chao-Wen Tzeng, Shi-Yu Huang:
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. IEEE Des. Test Comput. 25(2): 132-140 (2008) - [j3]Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang:
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ACM Trans. Design Autom. Electr. Syst. 13(1): 9:1-9:27 (2008) - [c1]Chao-Wen Tzeng, Shi-Yu Huang:
Two-Gear Low-Power Scan Test. ATS 2008: 337-342 - 2007
- [j2]Chao-Wen Tzeng, J.-J. Hsu, Shi-Yu Huang:
Robust paradigm for diagnosing hold-time faults in scan chains. IET Comput. Digit. Tech. 1(6): 706-715 (2007) - [j1]Chao-Wen Tzeng, Shi-Yu Huang:
Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain. IEEE Trans. Circuits Syst. II Express Briefs 54-II(8): 690-694 (2007)
Coauthor Index
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