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2020 – today
- 2023
[j4]Chia-Heng Yen
, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao:
CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4282-4295 (2023)- 2022
- [j3]Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5057-5070 (2022) - 2021
- [c12]Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao:
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS 2021: 1-7 - 2020
- [c11]Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS 2020: 1-6
2010 – 2019
- 2019
- [c10]Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC 2019: 1-10 - [c9]Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee:
Layout-Based Dual-Cell-Aware Tests. VTS 2019: 1-6 - 2018
- [j2]Chien-Hsueh Lin, Chih-Ying Tsai, Kao-Chi Lee, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2139-2151 (2018) - 2017
- [c8]Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Yang, Wen-Hsiang Chang, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques. ASP-DAC 2017: 426-431 - [c7]Yu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien, Ying-Yen Chen, Max Wu, Jih-Nung Lee, Mango C.-T. Chao:
Methodology of generating dual-cell-aware tests. VTS 2017: 1-6 - 2016
- [c6]Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
Predicting Vt mean and variance from parallel Id measurement with model-fitting technique. VTS 2016: 1-6 - 2015
- [c5]Chao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao:
Case study of process and design performance debugging with Digital Speed Sensor. VLSI-DAT 2015: 1-4 - 2014
- [j1]Po-Juei Chen, Chieh-Chih Che, J. C.-M. Li, Shuo-Fen Kuo, Pei-Ying Hsueh, Chun-Yi Kuo, Jih-Nung Lee:
Physical-aware systematic multiple defect diagnosis. IET Comput. Digit. Tech. 8(5): 199-209 (2014) - 2013
- [c4]Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu:
Case study of yield learning through in-house flow of volume diagnosis. VLSI-DAT 2013: 1-4
2000 – 2009
- 2009
- [c3]Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu:
A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. ITC 2009: 1-10 - 2003
- [c2]Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD 2003: 595-598 - [c1]Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories. ITC 2003: 29-38
Coauthor Index
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