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2020 – today
- 2023
[c8]Bing-Han Hsieh, Yun-Sheng Liu, James Chien-Mo Li, Chris Nigh, Mason Chern, Gaurav Bhargava:
Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis. ITC 2023: 293-302- 2022
- [j2]Yu-Teng Nien
, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5057-5070 (2022) - [c7]Cheng-Sian Kuo, Bing-Han Hsieh, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava, Mason Chern:
Diagnosing Double Faulty Chains through Failing Bit Separation. ITC 2022: 175-184 - 2021
- [c6]Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao:
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS 2021: 1-7 - 2020
- [j1]Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng:
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3044-3055 (2020) - [c5]Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS 2020: 1-6
2010 – 2019
- 2019
- [c4]Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng:
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. ASP-DAC 2019: 341-346 - [c3]Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao:
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC 2019: 1-10 - [c2]Tse-Wei Wu, Dong-Zhen Lee, Yu-Hao Huang, Mango C.-T. Chao, Kai-Chiang Wu, Shu-Yi Kao, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee:
Layout-Based Dual-Cell-Aware Tests. VTS 2019: 1-6 - 2017
- [c1]Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai:
Resilient Cell-Based Architecture for Time-to-Digital Converter. ISVLSI 2017: 7-12
Coauthor Index
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