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ORCID9. SASP 2011: San Diego, California, USA
- IEEE 9th Symposium on Application Specific Processors, SASP 2011, San Diego, CA, USA, June 5-6, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1211-1
- Maximilien Breughe, Zheng Li, Yang Chen, Stijn Eyerman, Olivier Temam, Chengyong Wu, Lieven Eeckhout:
How sensitive is processor customization to the workload's input datasets? 1-7 - Muhammad Shafiq
, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé:
TARCAD: A template architecture for reconfigurable accelerator designs. 8-15 - Liang Chen, Nicolas Boichat, Tulika Mitra:
Customized MPSoC synthesis for task sequence. 16-21 - Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Integrating formal verification and high-level processor pipeline synthesis. 22-29 - Adarsha Rao, S. K. Nandy, Hristo Nikolov, Ed F. Deprettere:
USHA: Unified software and hardware architecture for video decoding. 30-37 - Amin Farmahini Farahani, Anthony E. Gregerson, Michael J. Schulte, Katherine Compton:
Modular high-throughput and low-latency sorting units for FPGAs in the Large Hadron Collider. 38-45 - Bo Zhou, Xiaobo Sharon Hu, Danny Z. Chen:
Memory-efficient volume ray tracing on GPU for radiotherapy. 46-51 - Sergey Morozov, Christian Tergino, Patrick Schaumont:
System integration of Elliptic Curve Cryptography on an OMAP platform. 52-57 - Anthony Chun, Jenny X. Chang, Zhen Fang, Ravishankar R. Iyer, Michael Deisher:
ISIS: An accelerator for Sphinx speech recognition. 58-61 - Naim Harb, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Rabie Ben Atitallah:
Dynamically reconfigurable architecture for a driver assistant system. 62-65 - Rishvanth Kora Venugopal, J. Robert Heath, Daniel L. Lau:
FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm. 66-69 - Jason Cong, Muhuan Huang, Yi Zou:
3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applications. 70-73 - Hongjian Li, Bing Ni, Man Hon Wong, Kwong-Sak Leung:
A fast CUDA implementation of agrep algorithm for approximate nucleotide sequence matching. 74-77 - Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert:
Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration. 78-81 - Guohui Wang, Michael Wu, Yang Sun, Joseph R. Cavallaro:
A massively parallel implementation of QC-LDPC decoder on GPU. 82-85 - Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
ARTE: An Application-specific Run-Time management framework for multi-core systems. 86-93 - David Kesler, Biplab Deka, Rakesh Kumar:
A hardware acceleration technique for gradient descent and conjugate gradient. 94-101 - Tom Vander Aa, Martin Palkovic, Matthias Hartmann, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre:
A multi-threaded coarse-grained array processor for wireless baseband. 102-107 - Shuo-Hung Chen, Hsiao-Mei Lin, Hsin-Wen Wei, Yi-Cheng Chen, Chih-Tsun Huang, Yeh-Ching Chung:
Hardware/software co-designed accelerator for vector graphics applications. 108-114 - Chen Huang, Frank Vahid:
Scalable object detection accelerators on FPGAs using custom design space exploration. 115-121 - Abhinandan Majumdar, Srihari Cadambi, Srimat T. Chakradhar, Hans Peter Graf:
A parallel accelerator for semantic search. 122-128 - Roto Le, R. Iris Bahar, Joseph L. Mundy:
A novel parallel Tier-1 coder for JPEG2000 using GPUs. 129-136
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