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ORCIDEriko Nurvitadhi
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2020 – today
- 2024
[j18]Anupreetham Anupreetham
, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-Sun Seo:
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. ACM Trans. Reconfigurable Technol. Syst. 17(1): 1:1-1:20 (2024)- 2023
- [j17]Suyeon Hur, Seongmin Na, Dongup Kwon, Joonsung Kim, Andrew Boutros, Eriko Nurvitadhi, Jangwoo Kim:
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks. ACM Trans. Archit. Code Optim. 20(1): 11:1-11:24 (2023) - [j16]Zhipeng Zhao, Joseph Melber, Siddharth Sahay, Shashank Obla, Eriko Nurvitadhi, James C. Hoe:
Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA. IEEE Trans. Computers 72(5): 1343-1355 (2023) - [j15]Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(1): 4:1-4:26 (2023) - [i7]Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz:
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. CoRR abs/2301.04767 (2023) - 2022
- [j14]Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz:
Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices. IEEE Access 10: 95067-95082 (2022) - [j13]Rui Ma, Evangelos Georganas, Alexander Heinecke, Sergey Gribok, Andrew Boutros, Eriko Nurvitadhi:
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems. IEEE Comput. Archit. Lett. 21(2): 49-52 (2022) - [j12]Martin Langhammer, Eriko Nurvitadhi, Sergey Gribok, Bogdan Pasca:
Stratix 10 NX Architecture. ACM Trans. Reconfigurable Technol. Syst. 15(4): 45:1-45:32 (2022) - [j11]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk:
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 227-237 (2022) - [c54]Adel Ejjeh, Leon Medvinsky, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram S. Adve, Luigi Nardi, Eriko Nurvitadhi, Rob A. Rutenbar:
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming. ASAP 2022: 1-10 - [c53]Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz:
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. FPL 2022: 438-444 - [i6]Rui Ma, Evangelos Georganas, Alexander Heinecke, Andrew Boutros, Eriko Nurvitadhi:
FPGA-based AI Smart NICs for Scalable Distributed AI Training Systems. CoRR abs/2204.10943 (2022) - 2021
- [j10]Tian Tan, Eriko Nurvitadhi, Aravind Dasu, Martin Langhammer, Derek Chiou:
FlexScore: Quantifying Flexibility. IEEE Comput. Archit. Lett. 20(1): 58-61 (2021) - [j9]Jessica Vandebon, José Gabriel de Figueiredo Coutinho, Wayne Luk, Eriko Nurvitadhi:
Enhancing High-Level Synthesis Using a Meta-Programming Approach. IEEE Trans. Computers 70(12): 2043-2055 (2021) - [j8]Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu, Derek Chiou:
Specializing FGPU for Persistent Deep Learning. ACM Trans. Reconfigurable Technol. Syst. 14(2): 10:1-10:23 (2021) - [c52]Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das:
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM 2021: 88-96 - [c51]Martin Langhammer, Eriko Nurvitadhi, Bogdan Pasca, Sergey Gribok:
Stratix 10 NX Architecture and Applications. FPGA 2021: 57-67 - [c50]Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo:
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL 2021: 76-82 - [c49]Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, Rajesh Vivekanandham, Aravind Dasu, Martin Langhammer, Derek Chiou:
DO-GPU: Domain Optimizable Soft GPUs. FPL 2021: 140-144 - [c48]Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz:
Specializing for Efficiency: Customizing AI Inference Processors on FPGAs. ICM 2021: 62-65 - [c47]Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi R. Iyer, Li Zhao, Reetuparna Das:
Cache Compression with Efficient in-SRAM Data Comparison. NAS 2021: 1-8 - 2020
- [c46]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik:
SLATE: Managing Heterogeneous Cloud Functions. ASAP 2020: 141-148 - [c45]Dongup Kwon, Suyeon Hur, Hamin Jang, Eriko Nurvitadhi, Jangwoo Kim:
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels. DAC 2020: 1-6 - [c44]Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk:
Optimizing Reconfigurable Recurrent Neural Networks. FCCM 2020: 10-18 - [c43]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Tim Todman:
Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies. FCCM 2020: 177-185 - [c42]Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-Sun Seo:
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD 2020: 74:1-74:8 - [c41]Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer:
Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. FPT 2020: 10-19 - [c40]Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT 2020: 20-28
2010 – 2019
- 2019
- [j7]Tian Tan, Eriko Nurvitadhi, Derek Chiou:
Dark Wires and the Opportunities for Reconfigurable Logic. IEEE Comput. Archit. Lett. 18(1): 67-70 (2019) - [c39]Yu Wang, James C. Hoe, Eriko Nurvitadhi:
Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform. FCCM 2019: 136-144 - [c38]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu:
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM 2019: 199-207 - [c37]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu:
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA 2019: 119 - [c36]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL 2019: 166-172 - [c35]Rui Ma, Derek Chiou, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu:
Specializing FGPU for Persistent Deep Learning. FPL 2019: 326-333 - [c34]Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik:
Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity. FPT 2019: 162-170 - [c33]Eriko Nurvitadhi, Mishali Naik, Andrew Boutros, Prerna Budhkar, Ali Jafari, Dongup Kwon, David Sheffield, Abirami Prabhakaran, Karthik Gururaj, Pranavi Appana:
Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs. FPT 2019: 307-310 - [c32]Eriko Nurvitadhi:
FPGA-based Computing in the Era of AI and Big Data. ISPD 2019: 35 - [i5]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR abs/1908.06724 (2019) - 2018
- [c31]Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM 2018: 73-80 - [c30]Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong:
A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. FPGA 2018: 107-116 - [c29]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA 2018: 287 - [c28]Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA 2018: 294 - [c27]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL 2018: 106-110 - [c26]Tian Tan, Eriko Nurvitadhi, David Shih, Derek Chiou:
Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks. FPT 2018: 206-213 - [c25]Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr:
WRPN: Wide Reduced-Precision Networks. ICLR (Poster) 2018 - [i4]Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR abs/1806.11547 (2018) - 2017
- [c24]Asit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr:
Fine-grained accelerators for sparse machine learning workloads. ASP-DAC 2017: 635-640 - [c23]Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh:
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? FPGA 2017: 5-14 - [c22]Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong:
High performance binary neural networks on the Xeon+FPGA™ platform. FPL 2017: 1-4 - [c21]Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra:
Customizable FPGA OpenCL matrix multiply design template for deep neural networks. FPT 2017: 259-262 - [c20]Ganesh Venkatesh, Eriko Nurvitadhi, Debbie Marr:
Accelerating Deep Convolutional Networks using low-precision and sparsity. ICASSP 2017: 2861-2865 - [i3]Asit K. Mishra, Jeffrey J. Cook, Eriko Nurvitadhi, Debbie Marr:
WRPN: Training and Inference using Wide Reduced-Precision Networks. CoRR abs/1704.03079 (2017) - [i2]Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr:
WRPN: Wide Reduced-Precision Networks. CoRR abs/1709.01134 (2017) - 2016
- [c19]Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr:
Hardware accelerator for analytics of sparse data. DATE 2016: 1616-1621 - [c18]Gabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe:
A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems. FPGA 2016: 264-273 - [c17]Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr:
Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. FPL 2016: 1-4 - [c16]Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr:
Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. FPT 2016: 77-84 - [p1]Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen:
3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. Large-Scale Visual Geo-Localization 2016: 189-203 - [i1]Ganesh Venkatesh, Eriko Nurvitadhi, Debbie Marr:
Accelerating Deep Convolutional Networks using low-precision and sparsity. CoRR abs/1610.00324 (2016) - 2015
- [c15]Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr:
A sparse matrix vector multiply accelerator for support vector machine. CASES 2015: 109-116 - [c14]Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José F. Martínez, Rob A. Rutenbar:
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. FPL 2015: 1-8 - 2014
- [c13]Robert Tamburo, Eriko Nurvitadhi, Abhishek Chugh, Mei Chen, Anthony Rowe, Takeo Kanade, Srinivasa G. Narasimhan:
Programmable Automotive Headlights. ECCV (4) 2014: 750-765 - [c12]Eriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, José F. Martínez, Carlos Guestrin:
GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. FCCM 2014: 25-28 - 2013
- [c11]Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen:
3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. CVPR Workshops 2013: 229-236 - [c10]Abhishek A. Sharma, Kaustubh Neelathalli, Diana Marculescu, Eriko Nurvitadhi:
Hardware-efficient stereo estimation using a residual-based approach. ICASSP 2013: 2693-2696 - [c9]Eriko Nurvitadhi:
MEMOCODE 2013 hardware/software co-design contest: Stereo matching. MEMOCODE 2013: 131-134 - 2011
- [j6]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Automatic Pipelining From Transactional Datapath Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 441-454 (2011) - [c8]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Integrating formal verification and high-level processor pipeline synthesis. SASP 2011: 22-29 - 2010
- [c7]Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam:
Automatic multithreaded pipeline synthesis from transactional datapath specifications. DAC 2010: 314-319 - [c6]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Automatic pipelining from transactional datapath specifications. DATE 2010: 1001-1004
2000 – 2009
- 2009
- [j5]Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi:
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 15:1-15:32 (2009) - 2008
- [j4]Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu:
Active Cache Emulator. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 229-240 (2008) - [c5]Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai:
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA 2008: 77-86 - 2007
- [j3]Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Kim:
Adaptive semi-soft handoff for Cellular IP networks. Int. J. Wirel. Mob. Comput. 2(2/3): 109-119 (2007) - [c4]Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai:
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS 2007: 1-6 - 2006
- [c3]Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu:
Design, implementation, and verification of active cache emulator (ACE). FPGA 2006: 63-72 - 2005
- [j2]Ben Lee, Eriko Nurvitadhi, Reshma Dixit, Chansu Yu, Myungchul Kim:
Dynamic voltage scaling techniques for power efficient video decoding. J. Syst. Archit. 51(10-11): 633-652 (2005) - [j1]Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
TRUSS: A Reliable, Scalable Server Architecture. IEEE Micro 25(6): 51-59 (2005) - [c2]Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu:
Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. ICS 2005: 12-20 - 2003
- [c1]Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Kim:
A Comparative Study of Dynamic Voltage Scaling Techniques for Low-Power Video Decoding. Embedded Systems and Applications 2003: 292-298
Coauthor Index
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last updated on 2024-08-08 20:12 CEST by the dblp team
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