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2020 – today
- 2022
[c21]Dennis Abts, Ibrahim Ahmed, Andrew Bitar, Matthew Boyd, John Kim, Garrin Kimmell, Andrew C. Ling:
Challenges/Opportunities to Enable Dependable Scale-out System with Groq Deterministic Tensor-Streaming Processors. DSN (Supplements) 2022: 19-22- [c20]Dennis Abts, John Kim, Garrin Kimmell, Matthew Boyd, Kris Kang, Sahil Parmar, Andrew C. Ling, Andrew Bitar, Ibrahim Ahmed, Jonathan Ross:
The Groq Software-defined Scale-out Tensor Streaming Multiprocessor : From chips-to-systems architectural overview. HCS 2022: 1-69 - [c19]Dennis Abts, Garrin Kimmell, Andrew C. Ling, John Kim, Matthew Boyd, Andrew Bitar, Sahil Parmar, Ibrahim Ahmed, Roberto DiCecco, David Han, John Thompson, Michael Bye, Jennifer Hwang, Jeremy Fowers, Peter Lillian, Ashwin Murthy, Elyas Mehtabuddin, Chetan Tekur, Thomas Sohmers, Kris Kang, Stephen Maresh, Jonathan Ross:
A software-defined tensor streaming multiprocessor for large-scale machine learning. ISCA 2022: 567-580
2010 – 2019
- 2018
- [c18]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA 2018: 287 - [c17]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL 2018: 106-110 - [c16]Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu:
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. FPL 2018: 411-418 - [c15]Andrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu:
Harnessing Numerical Flexibility for Deep Learning on FPGAs. HEART 2018: 1:1-1:3 - [c14]Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah:
Flexibility: FPGAs and CAD in Deep Learning Acceleration. ISPD 2018: 34-41 - [i2]Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu:
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. CoRR abs/1807.06434 (2018) - 2017
- [c13]Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu:
An OpenCL™ Deep Learning Accelerator on Arria 10. FPGA 2017: 55-64 - [c12]Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra:
Customizable FPGA OpenCL matrix multiply design template for deep neural networks. FPT 2017: 259-262 - [c11]Andrew C. Ling, Utku Aydonat, Shane O'Connell, Davor Capalija, Gordon R. Chiu:
Creating High Performance Applications with Intel's FPGA OpenCL™ SDK. IWOCL 2017: 11:1 - [c10]Byron Sinclair, Andrew C. Ling, Genady Paikin:
Harnessing the Power of FPGAs with the Intel FPGA SDK for OpenCL™. IWOCL 2017: 19:1 - [i1]Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu:
An OpenCL(TM) Deep Learning Accelerator on Arria 10. CoRR abs/1701.03534 (2017) - 2013
- [c9]Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling:
Harnessing the power of FPGAs using altera's OpenCL compiler. FPGA 2013: 5-6 - 2011
- [j3]Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu:
Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 18-30 (2011) - 2010
- [c8]Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu:
Towards scalable placement for FPGAs. FPGA 2010: 147-156
2000 – 2009
- 2009
- [c7]Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour:
Towards automated ECOs in FPGAs. FPGA 2009: 3-12 - 2008
- [j2]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 423-435 (2008) - [c6]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI 2008: 163-166 - 2007
- [j1]Andrew C. Ling, Deshanand P. Singh
, Stephen Dean Brown:
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1196-1210 (2007) - [c5]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC 2007: 408-413 - [c4]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
Incremental placement for structured ASICs using the transportation problem. VLSI-SoC 2007: 172-177 - 2005
- [c3]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA technology mapping: a study of optimality. DAC 2005: 427-432 - [c2]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL 2005: 19-24 - [c1]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT 2005: 444-450
Coauthor Index
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