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ORCIDSean Safarpour
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- affiliation: University of Toronto, Canada
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2010 – 2019
- 2011
[j5]Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu:
Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 18-30 (2011)- [c26]Andreas G. Veneris, Brian Keng, Sean Safarpour:
From RTL to silicon: The case for automated debug. ASP-DAC 2011: 306-310 - [c25]Brian Keng, Sean Safarpour, Andreas G. Veneris:
Automated debugging of SystemVerilog assertions. DATE 2011: 323-328 - [c24]Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour:
Debugging with dominance: On-the-fly RTL debug solution implications. ICCAD 2011: 587-594 - 2010
- [j4]Brian Keng, Sean Safarpour, Andreas G. Veneris:
Bounded Model Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1790-1803 (2010) - [j3]Yibin Chen, Sean Safarpour, João Marques-Silva
, Andreas G. Veneris:
Automated Design Debugging With Maximum Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1804-1817 (2010) - [c23]Sean Safarpour, Andreas G. Veneris, Farid N. Najm:
Managing verification error traces with bounded model debugging. ASP-DAC 2010: 601-606 - [c22]Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour:
Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED 2010: 675-682 - [c21]Brian Keng, Andreas G. Veneris, Sean Safarpour:
An Automated Framework for Correction and Debug of PSL Assertions. MTV 2010: 9-12
2000 – 2009
- 2009
- [j2]Sean Safarpour, Andreas G. Veneris:
Automated Design Debugging With Abstraction and Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1597-1608 (2009) - [c20]Andreas G. Veneris, Sean Safarpour:
The day Sherlock Holmes decided to do EDA. DAC 2009: 631-634 - [c19]Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour:
Towards automated ECOs in FPGAs. FPGA 2009: 3-12 - [c18]Yibin Chen, Sean Safarpour, Andreas G. Veneris, João Marques-Silva:
Spatial and temporal design debug using partial MaxSAT. ACM Great Lakes Symposium on VLSI 2009: 345-350 - [c17]Sean Safarpour, Andreas G. Veneris:
Automated debugging with high level abstraction and refinement. HLDVT 2009: 26-31 - 2008
- [j1]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler:
Improved SAT-based Reachability Analysis with Observability Don't Cares. J. Satisf. Boolean Model. Comput. 5(1-4): 1-25 (2008) - 2007
- [c16]Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian:
Trace Compaction using SAT-based Reachability Analysis. ASP-DAC 2007: 932-937 - [c15]Sean Safarpour, Andreas G. Veneris:
Abstraction and refinement techniques in automated design debugging. DATE 2007: 1182-1187 - [c14]Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir:
Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543 - [c13]Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah:
Improved Design Debugging Using Maximum Satisfiability. FMCAD 2007: 13-19 - [c12]Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith:
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. ICCAD 2007: 240-245 - 2006
- [c11]Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan:
Efficient SAT-based Boolean matching for FPGA technology mapping. DAC 2006: 466-471 - [c10]Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler:
On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144 - [c9]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler:
Integrating observability don't cares in all-solution SAT solvers. ISCAS 2006 - [c8]Sean Safarpour, Andreas G. Veneris:
Abstraction and Refinement Techniques in Automated Design Debugging. MTV 2006: 88-93 - 2005
- [c7]Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour:
Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI 2005: 193-196 - [c6]Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler:
Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269 - [c5]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876 - [c4]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47 - 2004
- [c3]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee:
Managing Don't Cares in Boolean Satisfiability. DATE 2004: 260-265 - [c2]Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir:
Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209 - [c1]Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith:
Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49
Coauthor Index
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