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ORCID5th MTV 2004: Austin, TX, USA
- Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA. IEEE Computer Society 2004, ISBN 0-7695-2320-X
Introduction
- Preface.
- Acknowledgement.
- Workshop Organizing Committee.
- Program Committee.
Session A: Functional Test Generation
- Anshuman S. Nadkarni, Tom Kenville:
TiGeR, the Transmeta Instruction GEneratoR: A Production Based, Pseudo Random Instruction x86 Test Generator. 2-7 - W. Lindsay, Ernesto Sánchez, Matteo Sonza Reorda
, Giovanni Squillero:
Automatic Test Programs Generation Driven by Internal Performance Counters. 8-13
Session B: SOC Test
- Arkan Abdulrahman, Spyros Tragoudas:
Compact ATPG for Concurrent SOC Testing. 16-21 - Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda:
Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. 22-27
Session C: Modeling and Verification Method
- Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
Extreme Formal Modeling (XFM) for Hardware Models. 30-35 - Xiuli Sun, Jinzhao Wu, Xiaoyu Song, Mila E. Majster-Cederbaum:
Formal Specification of an Asynchronous Processor via Action Refinement. 36-41
Session D: SAT and Applications
- Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith:
Debugging Sequential Circuits Using Boolean Satisfiability. 44-49 - Marc Herbstritt, Thomas Kmieciak, Bernd Becker:
On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification. 50-55 - Tobias Schubert, Bernd Becker:
PICHAFF2 - A Hierarchical Parallel SAT Solver. 56-61
Session E: Functional Verification
- Mark Litterick, Joachim Geishauser:
Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments. 64-78 - Prabhat Mishra, Nikil D. Dutt, Yaron Kashai:
Functional Verification of Pipelined Processors: A Case Study. 79-84 - Michele Borgatti, Andrea Fedeli, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
A Verification Methodology for Reconfigurable Systems. 85-90
Session F: Advanced Test
- M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu:
Identification of Gates for Covering all Critical Paths. 92-96 - Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. 97-102 - Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. 103-109
Special Session G: Micro-Architecture Verification
- Eyal Bin, Laurent Fournier:
Micro-Architecture Verification for Microprocessors. 112-113
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