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ORCIDJianwen Zhu
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- affiliation: University of Toronto, Canada
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2020 – today
- 2024
[j11]Linglong Du, Jianwen Zhu, Feng Xie:
The Unconditional Consensus Control through Leadership for the Delayed Hegselmann-Krause Model. SIAM J. Control. Optim. 62(4): 2297-2318 (2024)- 2023
- [j10]Jianwen Zhu, Hao Zhang, Sibo Zhao, Weimin Bao:
Multi-constrained intelligent gliding guidance via optimal control and DQN. Sci. China Inf. Sci. 66(3) (2023) - 2020
- [c52]Reza Nakhjavani, Jianwen Zhu:
Rotary Register File: A Micro-Architectural Primitive on FPGA. FCCM 2020: 228
2010 – 2019
- 2017
- [c51]Reza Nakhjavani, Jianwen Zhu:
A Case for Common-Case: On FPGA Acceleration of Erasure Coding. FCCM 2017: 81 - [c50]Shu-Yi Jack Wong, Jianwen Zhu:
A fast Bayesian algorithmic enhancement for real time bit error ratio test (BERT). GlobalSIP 2017: 1310-1314 - 2016
- [j9]Yue Yang, Jianwen Zhu:
Write Skew and Zipf Distribution: Evidence and Implications. ACM Trans. Storage 12(4): 21:1-21:19 (2016) - [c49]Yue Yang, Jianwen Zhu:
Write Amplification with Write Skew. MASCOTS 2016: 406-411 - 2015
- [j8]Canwen Xiao
, Yue Yang, Jianwen Zhu:
A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks. IEEE Comput. Archit. Lett. 14(2): 111-114 (2015) - [c48]Yue Yang, Jianwen Zhu:
Algebraic modeling of write amplification in hotness-aware SSD. SYSTOR 2015: 4:1-4:11 - 2014
- [c47]Yue Yang, Jianwen Zhu:
Analytical modeling of garbage collection algorithms in hotness-aware flash-based solid state drives. MSST 2014: 1-10 - 2012
- [c46]Zefu Dai, Jianwen Zhu:
Saturating the transceiver bandwidth: switch fabric design on FPGAs. FPGA 2012: 67-76 - 2011
- [j7]Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu:
Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 18-30 (2011) - [c45]Yi Ni, Wai Sum Mong, Jianwen Zhu:
On virtual prototyping of embedded system-on-chips. ASICON 2011: 1106-1109 - [c44]Rami Beidas, Wai Sum Mong, Jianwen Zhu:
Register pressure aware scheduling for high level synthesis. ASP-DAC 2011: 461-466 - [c43]Zefu Dai, Jianwen Zhu:
A bursty multi-port memory controller with quality-of-service guarantees. CODES+ISSS 2011: 21-28 - [c42]Xun Chen, Jianwen Zhu:
Regular fabric for regular FPGA (abstract only). FPGA 2011: 284 - [c41]Xun Chen, Jianwen Zhu, Minxuan Zhang:
Timing-Driven Routing of High Fanout Nets. FPL 2011: 423-428 - 2010
- [c40]Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu:
Towards scalable placement for FPGAs. FPGA 2010: 147-156 - [c39]Zefu Dai, Nick Ni, Jianwen Zhu:
A 1 cycle-per-byte XML parsing accelerator. FPGA 2010: 199-208 - [c38]Alexander Choong, Rami Beidas, Jianwen Zhu:
Parallelizing Simulated Annealing-Based Placement Using GPGPU. FPL 2010: 31-34 - [c37]Zefu Dai, Mark Jarvin, Jianwen Zhu:
Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees. ICCAD 2010: 197-204 - [c36]Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu:
Using variable clocking to reduce leakage in synchronous circuits. ICCD 2010: 328-335 - [c35]Silvian Calman, Jianwen Zhu:
Interprocedural induction variable analysis based on interprocedural SSA form IR. PASTE 2010: 37-44
2000 – 2009
- 2009
- [c34]Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour:
Towards automated ECOs in FPGAs. FPGA 2009: 3-12 - [c33]Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu:
VariPipe: Low-overhead variable-clock synchronous pipelines. ICCD 2009: 117-124 - [c32]Silvian Calman, Jianwen Zhu:
Increasing the Scope and Resolution of Interprocedural Static Single Assignment. SAS 2009: 154-170 - 2008
- [j6]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 423-435 (2008) - [c31]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI 2008: 163-166 - 2007
- [c30]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC 2007: 408-413 - 2006
- [j5]Bin Wu, Jianwen Zhu, Farid N. Najm:
Dynamic-range estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1618-1636 (2006) - 2005
- [j4]Jianwen Zhu, Silvian Calman:
Context sensitive symbolic pointer analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 516-531 (2005) - [j3]Jianwen Zhu, Fang Fang, Qianying Tang:
Calligrapher: a new layout-migration engine for hard intellectual property libraries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1347-1361 (2005) - [c29]Rami Beidas, Jianwen Zhu:
Scalable interprocedural register allocation for high level synthesis. ASP-DAC 2005: 511-516 - [c28]Dennis Wu, Jianwen Zhu:
BDD-based two variable sharing extraction. ASP-DAC 2005: 1031-1034 - [c27]Jianwen Zhu:
Towards scalable flow and context sensitive pointer analysis. DAC 2005: 831-836 - [c26]Bin Wu, Jianwen Zhu, Farid N. Najm:
A non-parametric approach for dynamic range estimation of nonlinear systems. DAC 2005: 841-844 - [c25]Qianying Tang, Jianwen Zhu:
Two-Dimensional Layout Migration by Soft Constraint Satisfaction. ISQED 2005: 35-39 - 2004
- [c24]Zhong Wang, Jianwen Zhu:
Piecewise quadratic waveform matching with successive chord iteration. ASP-DAC 2004: 274-279 - [c23]Fang Fang, Jianwen Zhu:
Automatic process migration of datapath hard IP libraries. ASP-DAC 2004: 887-892 - [c22]Bin Wu, Jianwen Zhu, Farid N. Najm:
An analytical approach for dynamic range estimation. DAC 2004: 472-477 - [c21]Rami Beidas, Jianwen Zhu:
A queuing-theoretic performance model for context-flow system-on-chip platforms. ESTIMedia 2004: 21-26 - [c20]Massimo Poncino, Jianwen Zhu:
DynamoSim: a trace-based dynamically compiled instruction set simulator. ICCAD 2004: 131-136 - [c19]Bin Wu, Jianwen Zhu, Farid N. Najm:
Dynamic range estimation for nonlinear systems. ICCAD 2004: 660-667 - [c18]Fang Fang, Jianwen Zhu:
Calligrapher: A New Layout Migration Engine Based on Geometric Closeness. ISQED 2004: 25-30 - [c17]Khushwinder Jasrotia, Jianwen Zhu:
Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis. ISQED 2004: 425-430 - [c16]Jianwen Zhu, Silvian Calman:
Symbolic pointer analysis revisited. PLDI 2004: 145-157 - 2003
- [c15]Wai Sum Mong, Jianwen Zhu:
A retargetable micro-architecture simulator. DAC 2003: 752-757 - [c14]Jianwen Zhu, Wai Sum Mong:
Specification of Non-Functional Intellectual Property Components. DATE 2003: 10456-10461 - [c13]Zhong Wang, Jianwen Zhu:
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching. DATE 2003: 11026-11031 - [c12]Rami Beidas, Jianwen Zhu:
Performance Efficiency of Context-Flow System-on-Chip Platform. ICCAD 2003: 356-362 - 2002
- [j2]Jianwen Zhu, Daniel D. Gajski:
An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 363-373 (2002) - [c11]Maghsoud Abbaspour, Jianwen Zhu:
Retargetable binary utilities. DAC 2002: 331-336 - [c10]Khushwinder Jasrotia, Jianwen Zhu:
Hardware Implementation of a Memory Allocator. DSD 2002: 355-358 - [c9]Jianwen Zhu:
Symbolic pointer analysis. ICCAD 2002: 150-157 - 2001
- [c8]Jianwen Zhu, Daniel Gajski:
Compiling SpecC for simulation. ASP-DAC 2001: 57-62 - [c7]Jianwen Zhu:
MetaRTL: raising the abstraction level of RTL design. DATE 2001: 71-76 - [c6]Jianwen Zhu:
Static memory allocation by pointer analysis and coloring. DATE 2001: 785-790 - [c5]Jianwen Zhu, Edward S. Rogers Sr.:
Color Permutation: An Iterative Algorithm for Memory Packing. ICCAD 2001: 380-383
1990 – 1999
- 1999
- [c4]Jianwen Zhu, Daniel Gajski:
A unified formal model of ISA and FSMD. CODES 1999: 121-125 - [c3]Jianwen Zhu, Daniel Gajski:
Soft Scheduling in High Level Synthesis. DAC 1999: 219-224 - [c2]Jianwen Zhu, Daniel Gajski:
OpenJ: An Extensible System Level Design Language. DATE 1999: 480-484 - 1998
- [j1]Rainer Dömer, Daniel D. Gajski, Jianwen Zhu:
Specification and Design of Embedded Systems. Informationstechnik Tech. Inform. 40(3): 7-12 (1998) - [c1]Daniel Gajski, Rainer Dömer, Jianwen Zhu:
IP-Centric Methodology and Specification Language. DIPES 1998: 3-22
Coauthor Index
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