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2010 – 2019
- 2014
[c13]Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le:
Simulation and satisfiability guided counter-example triage for RTL design debugging. ISQED 2014: 618-624- 2013
- [c12]Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris:
A failure triage engine based on error trace signature extraction. IOLTS 2013: 73-78 - 2012
- [j3]Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici:
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1118-1131 (2012) - [c11]Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita:
Automated data analysis techniques for a modern silicon debug environment. ASP-DAC 2012: 298-303 - [c10]Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le:
Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE 2012: 292-295 - 2011
- [j2]Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 651-664 (2011) - 2010
- [c9]Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour:
Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED 2010: 675-682
2000 – 2009
- 2009
- [c8]Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris:
Automated data analysis solutions to silicon debug. DATE 2009: 982-987 - [c7]Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith:
Sequential logic rectifications with approximate SPFDs. DATE 2009: 1698-1703 - 2008
- [c6]Sobeeh Almukhaizim, Yiorgos Makris
, Yu-Shen Yang, Andreas G. Veneris:
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. IOLTS 2008: 123-128 - 2007
- [c5]Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Rectification by Approximate SPFDs. ASP-DAC 2007: 402-407 - 2006
- [j1]Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman:
Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 763-776 (2006) - [c4]Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris:
Seamless Integration of SER in Rewiring-Based Design Space Exploration. ITC 2006: 1-9 - 2005
- [c3]Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman:
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. DATE 2005: 996-1001 - 2003
- [c2]Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris:
Extraction Error Diagnosis and Correction in High-Performance Designs. ITC 2003: 423-430 - [c1]Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris:
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. MTV 2003: 54-59
Coauthor Index
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