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2020 – today
- 2020
[c12]Martin Langhammer, Sergey Gribok, Gregg Baeckler:
High Density 8-Bit Multiplier Systolic Arrays For Fpga. FCCM 2020: 84-92- [c11]Martin Langhammer, Sergey Gribok, Gregg Baeckler:
High Density Pipelined 8bit Multiplier Systolic Arrays for FPGA. FPGA 2020: 322 - [c10]Martin Langhammer, Gregg Baeckler, Sergey Gribok:
SpiderWeb - High Performance FPGA NoC. IPDPS Workshops 2020: 115-118
2010 – 2019
- 2019
- [c9]Martin Langhammer, Bogdan Pasca
, Gregg Baeckler:
High Precision, High Performance FPGA Adders. FCCM 2019: 298-306 - [c8]Martin Langhammer, Gregg Baeckler, Sergey Gribok:
Fractal Synthesis: Invited Tutorial. FPGA 2019: 202-211 - [c7]Martin Langhammer, Bogdan Pasca, Gregg Baeckler, Sergey Gribok:
Extracting INT8 Multipliers from INT18 Multipliers. FPL 2019: 114-120 - [i1]Sudarshan Srinivasan, Pradeep Janedula, Saurabh Dhoble, Sasikanth Avancha, Dipankar Das, Naveen Mellempudi, Bharat Daga, Martin Langhammer, Gregg Baeckler, Bharat Kaul:
High Performance Scalable FPGA Accelerator for Deep Neural Networks. CoRR abs/1908.11809 (2019) - 2018
- [c6]Martin Langhammer, Gregg Baeckler:
High Density and Performance Multiplication for FPGA. ARITH 2018: 5-12 - 2016
- [c5]Gregg Baeckler:
HyperPipelining of High-Speed Interface Logic. FPGA 2016: 2
2000 – 2009
- 2006
- [c4]Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan:
Efficient SAT-based Boolean matching for FPGA technology mapping. DAC 2006: 466-471 - [c3]Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo:
A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum 2006: 64-69 - 2005
- [c2]David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose:
The Stratix II logic and routing architecture. FPGA 2005: 14-20 - 2004
- [c1]Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini:
Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144
Coauthor Index
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