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ORCIDMohamed S. Abdelfattah
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2020 – today
- 2024
[c35]Xilai Dai, Yuzong Chen, Mohamed S. Abdelfattah:
FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision. FCCM 2024: 213- [c34]Xilai Dai, Yuzong Chen, Mohamed S. Abdelfattah:
Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision. FPL 2024: 156-163 - [c33]Jordan Dotzel, Bahaa Kotb, James Dotzel, Mohamed S. Abdelfattah, Zhiru Zhang:
Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel. Tiny Papers @ ICLR 2024 - [c32]Yash Akhauri, Mohamed S. Abdelfattah:
Encodings for Prediction-based Neural Architecture Search. ICML 2024 - [c31]Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang:
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. ICML 2024 - [c30]Lichuan Xiang, Lukasz Dudziak, Mohamed S. Abdelfattah, Abhinav Mehrotra, Nicholas Donald Lane, Hongkai Wen:
Towards Neural Architecture Search through Hierarchical Generative Modeling. ICML 2024 - [c29]Yash Akhauri, Mohamed S. Abdelfattah:
On Latency Predictors for Neural Architecture Search. MLSys 2024 - [i28]Rosco Hunter, Lukasz Dudziak, Mohamed S. Abdelfattah, Abhinav Mehrotra, Sourav Bhattacharya, Hongkai Wen:
Fast Inference Through The Reuse Of Attention Maps In Diffusion Models. CoRR abs/2401.01008 (2024) - [i27]Jordan Dotzel, Bahaa Kotb, James Dotzel, Mohamed S. Abdelfattah, Zhiru Zhang:
Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel. CoRR abs/2402.13536 (2024) - [i26]Yash Akhauri, Mohamed S. Abdelfattah:
On Latency Predictors for Neural Architecture Search. CoRR abs/2403.02446 (2024) - [i25]Yash Akhauri, Mohamed S. Abdelfattah:
Encodings for Prediction-based Neural Architecture Search. CoRR abs/2403.02484 (2024) - [i24]Ahmed F. AbouElhamayed, Susanne Balle, Deshanand P. Singh, Mohamed S. Abdelfattah:
Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision. CoRR abs/2403.12981 (2024) - [i23]Jordan Dotzel, Yash Akhauri, Ahmed S. AbouElhamayed, Carly Jiang, Mohamed S. Abdelfattah, Zhiru Zhang:
Radial Networks: Dynamic Layer Routing for High-Performance Large Language Models. CoRR abs/2404.04900 (2024) - [i22]Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang:
Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. CoRR abs/2405.03103 (2024) - [i21]Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah:
ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. CoRR abs/2406.16635 (2024) - [i20]Xilai Dai, Yuzong Chen, Mohamed S. Abdelfattah:
Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision. CoRR abs/2407.06033 (2024) - [i19]Yuzong Chen, Jian Meng, Jae-sun Seo, Mohamed S. Abdelfattah:
BBS: Bi-directional Bit-level Sparsity for Deep Learning Acceleration. CoRR abs/2409.05227 (2024) - 2023
- [j5]Erwei Wang
, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis:
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(4): 57:1-57:25 (2023) - [c28]Lichuan Xiang, Lukasz Dudziak, Mohamed S. Abdelfattah, Thomas C. P. Chau, Nicholas D. Lane, Hongkai Wen:
Zero-Cost Operation Scoring in Differentiable Architecture Search. AAAI 2023: 10453-10463 - [c27]Yash Akhauri, Mohamed S. Abdelfattah:
Multi-Predict: Few Shot Predictors For Efficient Neural Architecture Search. AutoML 2023: 23/1-23 - [c26]Yuzong Chen, Mohamed S. Abdelfattah:
BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs. FCCM 2023: 52-62 - [c25]Yuzong Chen, Jordan Dotzel, Mohamed S. Abdelfattah:
M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs. ICFPT 2023: 69-78 - [c24]Yassine Ghannane, Mohamed S. Abdelfattah:
DiviML: A Module-based Heuristic for Mapping Neural Networks onto Heterogeneous Platforms. ICCAD 2023: 1-9 - [i18]Yuzong Chen, Mohamed S. Abdelfattah:
BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs. CoRR abs/2304.03974 (2023) - [i17]Javier Fernández-Marqués, Ahmed F. AbouElhamayed, Nicholas D. Lane, Mohamed S. Abdelfattah:
Are We There Yet? Product Quantization and its Hardware Acceleration. CoRR abs/2305.18334 (2023) - [i16]Yash Akhauri, Mohamed S. Abdelfattah:
Multi-Predict: Few Shot Predictors For Efficient Neural Architecture Search. CoRR abs/2306.02459 (2023) - [i15]Yassine Ghannane, Mohamed S. Abdelfattah:
DiviML: A Module-based Heuristic for Mapping Neural Networks onto Heterogeneous Platforms. CoRR abs/2308.00127 (2023) - [i14]Jordan Dotzel, Gang Wu, Andrew Li, Muhammad Umar, Yun Ni, Mohamed S. Abdelfattah, Zhiru Zhang, Liqun Cheng, Martin G. Dixon, Norman P. Jouppi, Quoc V. Le, Sheng Li:
FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. CoRR abs/2308.03290 (2023) - [i13]Yuzong Chen, Jordan Dotzel, Mohamed S. Abdelfattah:
M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs. CoRR abs/2311.02758 (2023) - 2022
- [c23]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA 2022: 101-111 - [c22]Hongxiang Fan, Thomas Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah:
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. MICRO 2022: 599-615 - [c21]Thomas Chau, Lukasz Dudziak, Hongkai Wen, Nicholas D. Lane, Mohamed S. Abdelfattah:
BLOX: Macro Neural Architecture Search Benchmark and Algorithms. NeurIPS 2022 - [i12]Hongxiang Fan, Thomas Chun-Pong Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah:
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. CoRR abs/2209.09570 (2022) - [i11]Thomas Chun-Pong Chau, Lukasz Dudziak, Hongkai Wen, Nicholas Donald Lane, Mohamed S. Abdelfattah:
BLOX: Macro Neural Architecture Search Benchmark and Algorithms. CoRR abs/2210.07271 (2022) - 2021
- [c20]Lichuan Xiang, Royson Lee, Mohamed S. Abdelfattah, Nicholas D. Lane, Hongkai Wen:
Temporal Kernel Consistency for Blind Video Super-Resolution. ICCVW 2021: 3470-3479 - [c19]Mohamed S. Abdelfattah, Abhinav Mehrotra, Lukasz Dudziak, Nicholas Donald Lane:
Zero-Cost Proxies for Lightweight NAS. ICLR 2021 - [c18]Abhinav Mehrotra, Alberto Gil C. P. Ramos, Sourav Bhattacharya, Lukasz Dudziak, Ravichander Vipperla, Thomas Chau, Mohamed S. Abdelfattah, Samin Ishtiaq, Nicholas Donald Lane:
NAS-Bench-ASR: Reproducible Neural Architecture Search for Speech Recognition. ICLR 2021 - [c17]Qingqing Cao, Alexandru Eugen Irimiea, Mohamed S. Abdelfattah, Aruna Balasubramanian, Nicholas D. Lane:
Are Mobile DNN Accelerators Accelerating DNNs? EMDL@MobiSys 2021: 7-12 - [i10]Mohamed S. Abdelfattah, Abhinav Mehrotra, Lukasz Dudziak, Nicholas D. Lane:
Zero-Cost Proxies for Lightweight NAS. CoRR abs/2101.08134 (2021) - [i9]Lichuan Xiang, Lukasz Dudziak, Mohamed S. Abdelfattah, Thomas Chau, Nicholas D. Lane, Hongkai Wen:
Zero-Cost Proxies Meet Differentiable Architecture Search. CoRR abs/2106.06799 (2021) - [i8]Lichuan Xiang, Royson Lee, Mohamed S. Abdelfattah, Nicholas D. Lane, Hongkai Wen:
Temporal Kernel Consistency for Blind Video Super-Resolution. CoRR abs/2108.08305 (2021) - [i7]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR abs/2112.02346 (2021) - 2020
- [c16]Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. DAC 2020: 1-6 - [c15]Royson Lee, Lukasz Dudziak, Mohamed S. Abdelfattah, Stylianos I. Venieris, Hyeji Kim, Hongkai Wen, Nicholas D. Lane:
Journey Towards Tiny Perceptual Super-Resolution. ECCV (26) 2020: 85-102 - [c14]Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search. FPGA 2020: 315 - [c13]Abhinav Mehrotra, Lukasz Dudziak, Jinsu Yeo, Young-Yoon Lee, Ravichander Vipperla, Mohamed S. Abdelfattah, Sourav Bhattacharya, Samin Ishtiaq, Alberto Gil C. P. Ramos, SangJeong Lee, Daehyun Kim, Nicholas D. Lane:
Iterative Compression of End-to-End ASR Model Using AutoML. INTERSPEECH 2020: 3361-3365 - [c12]Lukasz Dudziak, Thomas Chau, Mohamed S. Abdelfattah, Royson Lee, Hyeji Kim, Nicholas D. Lane:
BRP-NAS: Prediction-based NAS using GCNs. NeurIPS 2020 - [i6]Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. CoRR abs/2002.05022 (2020) - [i5]Royson Lee, Lukasz Dudziak, Mohamed S. Abdelfattah, Stylianos I. Venieris, Hyeji Kim, Hongkai Wen, Nicholas D. Lane:
Journey Towards Tiny Perceptual Super-Resolution. CoRR abs/2007.04356 (2020) - [i4]Thomas Chau, Lukasz Dudziak, Mohamed S. Abdelfattah, Royson Lee, Hyeji Kim, Nicholas D. Lane:
BRP-NAS: Prediction-based NAS using GCNs. CoRR abs/2007.08668 (2020) - [i3]Abhinav Mehrotra, Lukasz Dudziak, Jinsu Yeo, Young-Yoon Lee, Ravichander Vipperla, Mohamed S. Abdelfattah, Sourav Bhattacharya, Samin Ishtiaq, Alberto Gil C. P. Ramos, SangJeong Lee, Daehyun Kim, Nicholas D. Lane:
Iterative Compression of End-to-End ASR Model using AutoML. CoRR abs/2008.02897 (2020)
2010 – 2019
- 2019
- [c11]Lukasz Dudziak, Mohamed S. Abdelfattah, Ravichander Vipperla, Stefanos Laskaridis, Nicholas D. Lane:
ShrinkML: End-to-End ASR Model Compression Using Reinforcement Learning. INTERSPEECH 2019: 2235-2239 - [i2]Lukasz Dudziak, Mohamed S. Abdelfattah, Ravichander Vipperla, Stefanos Laskaridis, Nicholas D. Lane:
ShrinkML: End-to-End ASR Model Compression Using Reinforcement Learning. CoRR abs/1907.03540 (2019) - 2018
- [c10]Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu:
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. FPL 2018: 411-418 - [c9]Andrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu:
Harnessing Numerical Flexibility for Deep Learning on FPGAs. HEART 2018: 1:1-1:3 - [c8]Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah:
Flexibility: FPGAs and CAD in Deep Learning Acceleration. ISPD 2018: 34-41 - [i1]Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu:
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. CoRR abs/1807.06434 (2018) - 2017
- [j4]Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz:
Design and Applications for Embedded Networks-on-Chip on FPGAs. IEEE Trans. Computers 66(6): 1008-1021 (2017) - 2016
- [j3]Mohamed S. Abdelfattah, Vaughn Betz:
Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 165-177 (2016) - [c7]Mohamed S. Abdelfattah, Vaughn Betz:
LYNX: CAD for FPGA-based networks-on-chip. FPL 2016: 1-10 - 2015
- [c6]Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz:
Take the Highway: Design for Embedded NoCs on FPGAs. FPGA 2015: 98-107 - [c5]Mohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz:
Design and simulation tools for Embedded NOCs on FPGAs. FPL 2015: 1 - [c4]Andrew Bitar, Mohamed S. Abdelfattah, Vaughn Betz:
Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA. FPT 2015: 24-31 - 2014
- [j2]Mohamed S. Abdelfattah, Vaughn Betz:
The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays. IEEE Micro 34(1): 80-89 (2014) - [j1]Mohamed S. Abdelfattah, Vaughn Betz:
Networks-on-Chip for FPGAs: Hard, Soft or Mixed? ACM Trans. Reconfigurable Technol. Syst. 7(3): 20:1-20:22 (2014) - [c3]Mohamed S. Abdelfattah, Andrei Hagiescu, Deshanand P. Singh:
Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL. IWOCL 2014: 4:1-4:9 - 2013
- [c2]Mohamed S. Abdelfattah, Vaughn Betz:
The power of communication: Energy-efficient NOCS for FPGAS. FPL 2013: 1-8 - 2012
- [c1]Mohamed S. Abdelfattah, Vaughn Betz:
Design tradeoffs for hard and soft FPGA-based Networks-on-Chip. FPT 2012: 95-103
Coauthor Index
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