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ORCIDICCAD 2023: San Francisco, CA, USA
- IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023. IEEE 2023, ISBN 979-8-3503-2225-5
- Boyu Long
, Libo Shen, Xiaoyu Zhang, Yinhe Han, Xian-He Sun, Xiaoming Chen:
Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis. 1-9 - Huifeng Zhu, Weidong Cao, Xuan Zhang:
PDNSig: Identifying Multi-Tenant Cloud FPGAs with Power Distribution Network-Based Signatures. 1-8 - Chih-Ting Lo, Yun-Chih Chen, Yuan-Hao Chang, Tei-Wei Kuo:
HAPIC: A Scalable, Lightweight and Reactive Cache for Persistent-Memory-Based Index. 1-7 - Chung-Chia Lee, Yao-Wen Chang:
Floorplanning for Embedded Multi-Die Interconnect Bridge Packages. 1-8 - Rongjian Liang, Anthony Agnesina, Geraldo Pradipta, Vidya A. Chhabria, Haoxing Ren:
Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization. 1-6 - Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh:
FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow. 1-9 - Florentia Afentaki, Gurol Saglam, Argyris Kokkinis, Kostas Siozios, Georgios Zervakis, Mehdi B. Tahoori:
Bespoke Approximation of Multiplication-Accumulation and Activation Targeting Printed Multilayer Perceptrons. 1-9 - Jialin Liu, Houman Homayoun, Chongzhou Fang, Ning Miao, Han Wang:
Side Channel-Assisted Inference Attacks on Machine Learning-Based ECG Classification. 1-9 - Muhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha, Hao Zheng, Rickard Ewetz:
Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications. 1-9 - Jinghao Ding, Linhao Lu, Zhaoqi Fu, Jie Ma, Mengshi Gong, Yuanrui Qi, Wenxin Yu:
Clock Aware Low Power Placement. 1-8 - Yan-Lin Chen, Wei-Che Tseng, Wei-Yao Kao, Yao-Wen Chang:
A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology Designs. 1-7 - Seonghyeon Park, Daeyeon Kim, Seongbin Kwon, Seokhyeong Kang:
Routability Prediction and Optimization Using Explainable AI. 1-8 - Shu-Ting Cheng, Wen Sheng Lim, Chia-Heng Tu, Yuan-Hao Chang:
TRAIN: A Reinforcement Learning Based Timing-Aware Neural Inference on Intermittent Systems. 1-9 - Yihan Wen, Juan Li, Xiaoyi Wang:
Risk Propagation Based Vector Profiling for High Coverage Dynamic IR-Drop Analysis. 1-8 - Jaehoon Heo, Yongwon Shin, Sangjin Choi, Sungwoong Yune, Jung-Hoon Kim, Hyojin Sung, Youngjin Kwon, Joo-Young Kim:
PRIMO: A Full-Stack Processing-in-DRAM Emulation Framework for Machine Learning Workloads. 1-9 - Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong, Cheng Zhuo:
BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer Learning. 1-9 - Hanyu Wang, Carmine Rizzi, Lana Josipovic:
MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. 1-9 - Arman Ferdowsi, Ulrich Schmid, Josef Salzmann:
Accurate Hybrid Delay Models for Dynamic Timing Analysis. 1-9 - Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang:
Invited Paper: Overview of 2023 CAD Contest at ICCAD. 1-6 - Stefan Abi-Karam, Rishov Sarkar, Dejia Xu, Zhiwen Fan, Zhangyang Wang, Cong Hao:
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing. 1-9 - Rishov Sarkar, Hanxue Liang, Zhiwen Fan, Zhangyang Wang, Cong Hao:
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-Level Sparsity via Mixture-of-Experts. 1-9 - Changdi Yang, Yi Sheng, Peiyan Dong, Zhenglun Kong, Yanyu Li, Pinrui Yu, Lei Yang, Xue Lin, Yanzhi Wang:
Fast and Fair Medical AI on the Edge Through Neural Architecture Search for Hybrid Vision Models. 1-9 - Rahul Vishwakarma, Amin Rezaei:
Risk-Aware and Explainable Framework for Ensuring Guaranteed Coverage in Evolving Hardware Trojan Detection. 1-9 - Yang Ni, Hanning Chen, Prathyush Poduval, Zhuowen Zou, Pietro Mercati, Mohsen Imani:
Brain-Inspired Trustworthy Hyperdimensional Computing with Efficient Uncertainty Quantification. 1-9 - Md Hafizul Islam Chowdhuryy, Zhenkai Zhang, Fan Yao:
BeKnight: Guarding Against Information Leakage in Speculatively Updated Branch Predictors. 1-9 - Mingfei Yu, Giovanni De Micheli:
Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled Circuits. 1-9 - Animesh Basak Chowdhury, Shailja Thakur, Hammond Pearce, Ramesh Karri, Siddharth Garg:
Invited Paper: Towards the Imagenets of ML4EDA. 1-7 - Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi:
LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory. 1-9 - Qijun Zhang, Shiyu Li, Guanglei Zhou, Jingyu Pan, Chen-Chia Chang, Yiran Chen, Zhiyao Xie:
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions. 1-9 - Yilun Zhao, Yu Chen, He Li, Ying Wang, Kaiyan Chang, Bingmeng Wang, Bing Li, Yinhe Han:
Full State Quantum Circuit Simulation Beyond Memory Limit. 1-9 - Muhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha, Rickard Ewetz:
Automated Synthesis for In-Memory Computing. 1-9 - Hamza Errahmouni Barkam, SungHeon Eavn Jeon, Sanggeon Yun, Calvin Yeung, Zhuowen Zou, Xun Jiao, Narayan Srinivasa, Mohsen Imani:
Invited Paper: Hyperdimensional Computing for Resilient Edge Learning. 1-8 - Tianshi Xu, Meng Li, Runsheng Wang, Ru Huang:
Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network Inference. 1-9 - Gauthaman Murali, Aditya Iyer, Navneeth Ravichandran, Sung Kyu Lim:
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators. 1-9 - Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. 1-9 - Chun-An Lee, Wen-Hao Liu, Gary Lin, Tsung-Yi Ho:
Delay-Matching Routing for Advanced Packages. 1-8 - Shreesha Sreedhara, Jaijeet Roychowdhury, Joachim Wabnig, Pavan Koteshwar Srinath:
MU-MIMO Detection Using Oscillator Ising Machines. 1-9 - Minwoo Kang, Azade Nova, Eshan Singh, Geetheeka Sharron Bathini, Yuriy Viktorov:
LFPS: Learned Formal Proof Strengthening for Efficient Hardware Verification. 1-9 - Juyeon Kim, Changho Han, Cheoljun Bae, Yoobeom Kim, Jae Hoon Kim, Hyungjung Seo:
Local Layout Effect-Aware Static Timing Analysis by use of a New Sensitivity-Based Library. 1-6 - Jiang Hu, Andrew B. Kahng:
Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff. 1-7 - Subed Lamichhane, Wentian Jin, Liang Chen, Mohammadamir Kavousi, Sheldon X.-D. Tan:
PostPINN-EM: Fast Post-Voiding Electromigration Analysis Using Two-Stage Physics-Informed Neural Networks. 1-9 - Andrija Neskovic, Saleh Mulhem, Alexander Treff, Rainer Buchty, Thomas Eisenbarth, Mladen Berekovic:
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not? 1-8 - Naina Gupta, Arpan Jati, Anupam Chattopadhyay:
CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital Signature. 1-7 - Yanfang Liu, Guohao Dai, Yuanqing Cheng, Wang Kang, Wei W. Xing:
OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits. 1-9 - Weihua Xiao, Shanshan Han, Yue Yang, Shaoze Yang, Cheng Zheng, Jingsong Chen, Tingyuan Liang, Lei Li, Weikang Qian:
MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network. 1-9 - Qiao Yu, Wengui Zhang, Jorge Cardoso, Odej Kao:
Exploring Error Bits for Memory Failure Prediction: An In-Depth Correlative Study. 1-9 - Ruiyao Pu, Yiwei Sun, Pei-Hsin Ho, Fan Yang, Li Shang, Xuan Zeng:
Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System. 1-9 - Yihao Yang, Pengfei Qiu, Chunlu Wang, Yu Jin, Qiang Gao, Xiaoyong Li, Dongsheng Wang, Gang Qu:
Exploration and Exploitation of Hidden PMU Events. 1-9 - Liang Chen, Jincong Lu, Wentian Jin, Sheldon X.-D. Tan:
Fast Full-Chip Parametric Thermal Analysis Based on Enhanced Physics Enforced Neural Networks. 1-8 - Rongliang Fu, Olivia Chen, Bei Yu, Nobuyuki Yoshikawa, Tsung-Yi Ho:
DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. 1-8 - Xikun Jiang, Zhaoyan Shen, Siqing Sun, Ping Yin, Zhiping Jia, Lei Ju, Zhiyong Zhang, Dongxiao Yu:
Runtime Row/Column Activation Pruning for ReRAM-based Processing-in-Memory DNN Accelerators. 1-9 - Yifan Chen, Zaiwen Wen, Yun Liang, Yibo Lin:
Stronger Mixed-Size Placement Backbone Considering Second-Order Information. 1-9 - Dake Chen, Yuke Zhang, Souvik Kundu, Chenghao Li, Peter A. Beerel:
RNA-ViT: Reduced-Dimension Approximate Normalized Attention Vision Transformers for Latency Efficient Private Inference. 1-9 - Peiyu Wang, Anqi Lu, Xing Li, Junjie Ye, Lei Chen, Mingxuan Yuan, Jianye Hao, Junchi Yan:
EasyMap: Improving Technology Mapping via Exploration-Enhanced Heuristics and Adaptive Sequencing. 1-9 - Changchun Zhou, Yuzhe Fu, Min Liu, Siyuan Qiu, Ge Li, Yifan He, Hailong Jiao:
An Energy-Efficient 3D Point Cloud Neural Network Accelerator With Efficient Filter Pruning, MLP Fusion, and Dual-Stream Sampling. 1-9 - Hyunsung Yoon, Jae-Joon Kim:
Efficient Sampling and Grouping Acceleration for Point Cloud Deep Learning via Single Coordinate Comparison. 1-9 - Jiaqi Yin, Cunxi Yu:
Accelerating Exact Combinatorial Optimization via RL-based Initialization - A Case Study in Scheduling. 1-9 - Sven Thijssen, Suraj Singireddy, Muhammad Rashedul Haq Rashed, Sumit Kumar Jha, Rickard Ewetz:
Verification of Flow-Based Computing Systems Using Bounded Model Checking. 1-9 - Wuwei Tian, Xinghui Jia, Siwei Tan, Zixuan Song, Liqiang Lu, Jianwei Yin:
QPulseLib: Accelerating the Pulse Generation of Quantum Circuit with Reusable Patterns. 1-9 - Yassine Ghannane, Mohamed S. Abdelfattah:
DiviML: A Module-based Heuristic for Mapping Neural Networks onto Heterogeneous Platforms. 1-9 - Andrew Cannon, Tasnuva Farheen, Sourav Roy, Shahin Tajik, Domenic Forte:
Protection Against Physical Attacks Through Self-Destructive Polymorphic Latch. 1-9 - Zhiyang Chen, Tsung-Yi Ho, Ulf Schlichtmann, Datao Chen, Mingyu Liu, Hailong Yao, Xia Yin:
NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network. 1-9 - Zonghao Li, Anthony Chan Carusone:
Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process. 1-9 - Prasanna Ravi, Dirmanto Jap, Shivam Bhasin, Anupam Chattopadhyay:
Invited Paper: Machine Learning Based Blind Side-Channel Attacks on PQC-Based KEMs - A Case Study of Kyber KEM. 1-7 - Xi Xie, Hongwu Peng, Amit Hasan, Shaoyi Huang, Jiahui Zhao, Haowen Fang, Wei Zhang, Tong Geng, Omer Khan, Caiwen Ding:
Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks. 1-9 - Wenxun Wang, Shuchang Zhou, Wenyu Sun, Peiqin Sun, Yongpan Liu:
SOLE: Hardware-Software Co-design of Softmax and LayerNorm for Efficient Transformer Inference. 1-9 - Muhammad Monir Hossain, Nusrat Farzana Dipu, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing. 1-9 - Dongxu Lyu, Zhenyu Li, Yuzhou Chen, Jinming Zhang, Ningyi Xu, Guanghui He:
SpOctA: A 3D Sparse Convolution Accelerator with Octree-Encoding-Based Map Search and Inherent Sparsity-Aware Processing. 1-9 - David Clarino, Naoya Asada, Shigeru Yamashita:
Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations. 1-8 - Zhengyuan Shi, Min Li, Yi Liu, Sadaf Khan, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Qiang Xu:
SATformer: Transformer-Based UNSAT Core Learning. 1-4 - Kai-Ting Weng, Yun-Shan Hsieh, Yen-Ting Chen, Yu-Pei Liang, Yuan-Hao Chang, Po-Chun Huang, Wei-Kuan Shih:
HF-Dedupe: Hierarchical Fingerprint Scheme for High Efficiency Data Deduplication on Flash-based Storage Systems. 1-9 - Charalampos Eleftheriadis, Georgios Karakonstantis:
ACOR: On the Design of Energy-Efficient Autocorrelation for Emerging Edge Applications. 1-9 - Qian Huang, Gaoxing Shang, Yu Zhang, Gang Chen:
EDS-SLAM: An Energy-Efficient Accelerator for Real-Time Dense Stereo SLAM with Learned Feature Matching. 1-9 - Jinwook Jung, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Dooseok Yoon:
Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research. 1-7 - Yizhen Lu, Luyang Yu, Deming Chen:
SSDe: FPGA-Based SSD Express Emulation Framework. 1-9 - Shengxi Shou, Che-Kai Liu, Sanggeon Yun, Zishen Wan, Kai Ni, Mohsen Imani, X. Sharon Hu, Jianyi Yang, Cheng Zhuo, Xunzhao Yin:
SEE-MCAM: Scalable Multi-Bit FeFET Content Addressable Memories for Energy Efficient Associative Search. 1-9 - Chris Lavin, Eddie Hung:
Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling. 1-7 - Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu:
Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. 1-4 - Hailiang Hu, Donghao Fang, Wuxi Li, Bo Yuan, Jiang Hu:
Systolic Array Placement on FPGAs. 1-9 - Cheng Wang, Mingyu Gao:
SAM: A Scalable Accelerator for Number Theoretic Transform Using Multi-Dimensional Decomposition. 1-9 - Ziyu Liu, Yukui Luo, Shijin Duan, Tong Zhou, Xiaolin Xu:
MirrorNet: A TEE-Friendly Framework for Secure On-Device DNN Inference. 1-9 - Kai-Shun Hu, Hao-Yu Chi, I-Jye Lin, Yi-Hsuan Wu, Wei-Hsu Chen, Yi-Ting Hsieh:
Invited Paper: 2023 ICCAD CAD Contest Problem B: 3D Placement with Macros. 1-6 - Johnny Rhe, Kang Eun Jeon, Joo Chan Lee, Seongmoon Jeong, Jong Hwan Ko:
Kernel Shape Control for Row-Efficient Convolution on Processing-In-Memory Arrays. 1-9 - Yueyin Bai, Hao Zhou, Keqing Zhao, Hongji Wang, Jianli Chen, Jun Yu, Kun Wang:
FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks. 1-9 - Zhuoping Yang, Jinming Zhuang, Jiaqi Yin, Cunxi Yu, Alex K. Jones, Peipei Zhou:
AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP. 1-9 - Juejian Wu, Tianyu Liao, Taixin Li, Yixin Xu, Vijaykrishnan Narayanan, Yongpan Liu, Huazhong Yang, Xueqing Li:
Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices. 1-9 - Jiteshri Dasari, Maciej J. Ciesielski:
Efficient Formal Verification and Debugging of Arithmetic Divider Circuits. 1-9 - Cheng-Hsiang Chiu, Dian-Lun Lin, Tsung-Wei Huang:
Invited Paper: Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms. 1-8 - Chengeng Li, Fan Jiang, Shixi Chen, Xianbin Li, Yinyi Liu, Lin Chen, Xiao Li, Jiang Xu:
RONet: Scaling GPU System with Silicon Photonic Chiplet. 1-9 - Jiacong Sun, Pouya Houshmand, Marian Verhelst:
Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling. 1-9 - Yaoxiu Lian, Xinhao Yang, Ke Hong, Yu Wang, Guohao Dai, Ningyi Xu:
A Point Transformer Accelerator with Fine-Grained Pipelines and Distribution-Aware Dynamic FPS. 1-9 - Gana Surya Prakash Kadagala, Vidya A. Chhabria:
Invited Paper: 2023 ICCAD CAD Contest Problem C: Static IR Drop Estimation Using Machine Learning. 1-5 - Alexander El-Kady, Apostolos P. Fournaris, Vassilis Paliouras:
Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis. 1-7 - Siyuan Liang, Meng Lian, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
ARMM: Adaptive Reliability Quantification Model of Microfluidic Designs and its Graph-Transformer-Based Implementation. 1-9 - Ahmed Agiza, Rajarshi Roy, Teodor-Dumitru Ene, Saad Godil, Sherief Reda, Bryan Catanzaro:
GraPhSyM: Graph Physical Synthesis Model. 1-9 - Jun Liu, Guohao Dai, Hao Xia, Lidong Guo, Xiangsheng Shi, Jiaming Xu, Huazhong Yang, Yu Wang:
TSTC: Two-Level Sparsity Tensor Core Enabling both Algorithm Flexibility and Hardware Efficiency. 1-9 - Gulsum Gudukbay Akbulut, Mahmut T. Kandemir, Mustafa Karaköy, Wonil Choi:
Data Recomputation for Multithreaded Applications. 1-9 - Xiuping Cui, Size Zheng, Tianyu Jia, Le Ye, Yun Liang:
ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions. 1-9 - Juseong Park, Yongwon Shin, Hyojin Sung:
Multi-Objective Architecture Search and Optimization for Heterogeneous Neuromorphic Architecture. 1-8 - Yongliang Chen, Xiaole Cui, Pengyuan Yang, Gang Qu:
An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates. 1-9 - Christian Krieg:
Reflections on Trusting TrustHUB. 1-9 - Yonghe Zhang, Liwei Ni, Jiaxi Zhang, Guojie Luo, Huawei Li, Shenggen Zheng:
Fast Exact NPN Classification with Influence-Aided Canonical Form. 1-9 - Rongliang Fu, Olivia Chen, Nobuyuki Yoshikawa, Tsung-Yi Ho:
Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic. 1-9 - Jai-Ming Lin, Yu-Chien Lin, Hsuan Kung, Wei-Yuan Lin:
HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique. 1-8 - Wendong Zheng, Yu Zhou, Gang Chen, Zonghua Gu, Kai Huang:
Towards Effective Training of Robust Spiking Recurrent Neural Networks Under General Input Noise via Provable Analysis. 1-9 - Mengyuan Li, Haoran Geng, Michael T. Niemier, Xiaobo Sharon Hu:
Accelerating Polynomial Modular Multiplication with Crossbar-Based Compute-in-Memory. 1-9 - Wei-Lun Chen, Fang-Yi Gu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann:
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing. 1-9 - Yoon Hyeok Lee, Youngmin Oh, Gyohun Jeong, Mingyu Pi, Hyukil Kwon, Hakyoung Lim, Eungchae Kim, Sunghee Lee, Bosun Hwang:
GRAFT: Graph-Assisted Reinforcement Learning for Automated SSD Firmware Testing. 1-8 - Jiahui Xu, Lana Josipovic:
Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. 1-9 - Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu, Kei-Yong Khoo:
Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching. 1-4 - Zhengyuan Shi, Hongyang Pan, Sadaf Khan, Min Li, Yi Liu, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Zhufei Chu, Qiang Xu:
DeepGate2: Functionality-Aware Circuit Representation Learning. 1-9 - Su Zheng, Lancheng Zou, Peng Xu, Siting Liu, Bei Yu, Martin D. F. Wong:
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction. 1-9 - Je-Woo Jang, Thai-Hoang Nguyen, Joon-Sung Yang:
VECOM: Variation-Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM-Based DNN Accelerator. 1-9 - Xiang Zhang, Aidong Adam Ding, Yunsi Fei:
Deep-Learning Model Extraction Through Software-Based Power Side-Channel. 1-9 - Christian Dietrich, Tim-Marek Thomas, Matthias Mnich:
Checkpoint Placement for Systematic Fault-Injection Campaigns. 1-9 - Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar:
Frequency-Domain Transient Electromigration Analysis Using Circuit Theory. 1-8 - Xueyan Zhao, Shijian Chen, Yihang Qiu, Jiangkao Li, Zhipeng Huang, Biwei Xie, Xingquan Li, Yungang Bao:
iPL-3D: A Novel Bilevel Programming Model for Die-to-Die Placement. 1-9 - Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren:
Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation. 1-8 - Haomin Li, Fangxin Liu, Yichi Chen, Li Jiang:
HyperNode: An Efficient Node Classification Framework Using HyperDimensional Computing. 1-9 - Jaewoo Park, Chenghao Quan, Hyungon Moon, Jongeun Lee:
Hyperdimensional Computing as a Rescue for Efficient Privacy-Preserving Machine Learning-as-a-Service. 1-8 - Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang:
READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction. 1-9 - Jincong Lu, Jinwei Zhang, Sheldon X.-D. Tan:
Real-time Thermal Map Estimation for AMD Multi-Core CPUs Using Transformer. 1-7 - Yuichi Sugiyama, Reoma Matsuo, Ryota Shioya:
SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs. 1-9 - Xuan Wang, Zheyu Yan, Chang Meng, Yiyu Shi, Weikang Qian:
DASALS: Differentiable Architecture Search-Driven Approximate Logic Synthesis. 1-9 - Yang Sui, Minning Zhu, Lingyi Huang, Chung-Tse Michael Wu, Bo Yuan:
Invited Paper: In-Sensor Radio Frequency Computing for Energy-Efficient Intelligent Radar. 1-9 - Zheyu Yan, Yifan Qin, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi:
Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise. 1-9 - Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li:
DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. 1-9 - Ivan De Oliveira Nunes, Seoyeon Hwang, Sashidhar Jakkamsetti, Norrathep Rattanavipanon, Gene Tsudik:
$\mathcal{P}\text{ARseL}$: Towards a Verified Root-of-Trust Over seL4. 1-9 - Younggwang Jung, Daijoon Hyun, Soyoon Choi, Youngsoo Shin:
Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement. 1-8 - Jialin Cao, Xuanda Lin, Manting Zhang, Kejia Shi, Jun Yu, Kun Wang:
PP-Transformer: Enable Efficient Deployment of Transformers Through Pattern Pruning. 1-9 - Libo Shen, Boyu Long, Rui Liu, Xiaoyu Zhang, Yinhe Han, Xiaoming Chen:
LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture. 1-9 - Weihang Tan, Yingjie Lao, Keshab K. Parhi:
KyberMat: Efficient Accelerator for Matrix-Vector Polynomial Multiplication in CRYSTALS-Kyber Scheme via NTT and Polyphase Decomposition. 1-9 - Duo Wang, Mingyu Yan, Yihan Teng, Dengke Han, Haoran Dang, Xiaochun Ye, Dongrui Fan:
A Transfer Learning Framework for High-Accurate Cross-Workload Design Space Exploration of CPU. 1-9 - Fuxing Huang, Duanxiang Liu, Xingquan Li, Bei Yu, Wenxing Zhu:
Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning. 1-9 - Yu Feng, Tianrui Ma, Adith Boloor, Yuhao Zhu, Xuan Zhang:
Invited Paper: Learned In-Sensor Visual Computing: From Compression to Eventification. 1-9 - Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz:
Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. 1-9 - Alireza Khataei, Kia Bazargan:
Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary Computing. 1-7 - Shubham Kumar, Yogesh Singh Chauhan, Hussam Amrouch:
Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D Integration. 1-6 - Junyao Wang, Luke Chen, Mohammad Abdullah Al Faruque:
DOMINO: Domain-Invariant Hyperdimensional Classification for Multi-Sensor Time Series Data. 1-9 - Yuntao Wei, Xueyan Wang, Song Bian, Weisheng Zhao, Yier Jin:
THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic Execution. 1-9 - Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong:
Robust GNN-Based Representation Learning for HLS. 1-9 - Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu:
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. 1-9 - Hao Fu, Mingzheng Zhu, Jun Wu, Wei Xie, Zhaofeng Su, Xiang-Yang Li:
Effective and Efficient Qubit Mapper. 1-9 - Sanjiang Li, Ky Dan Nguyen, Zachary Clare, Yuan Feng:
Single-Qubit Gates Matter for Optimising Quantum Circuit Depth in Qubit Mapping. 1-9 - Zhiqiang Liu, Wenjian Yu:
Accuracy-Preserving Reduction of Sparsified Reduced Power Grids with A Multilevel Node Aggregation Scheme. 1-9 - Suwan Kim, Taewhan Kim:
Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops. 1-9 - Zhihan Chen, Xindi Zhang, Yuhang Qian, Qiang Xu, Shaowei Cai:
Integrating Exact Simulation into Sweeping for Datapath Combinational Equivalence Checking. 1-9 - Amro Eldebiky, Bing Li, Grace Li Zhang:
NearUni: Near-Unitary Training for Efficient Optical Neural Networks. 1-8 - Da-Wei Huang, Ying-Jie Jiang, Shao-Yun Fang:
Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM Considerations. 1-8 - Xiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang, Yun Liang:
Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators. 1-9 - Yushu Wu, Yifan Gong, Zheng Zhan, Geng Yuan, Yanyu Li, Qi Wang, Chao Wu, Yanzhi Wang:
MOC: Multi-Objective Mobile CPU-GPU Co-Optimization for Power-Efficient DNN Inference. 1-10 - Ya Gao, Haocheng Ma, Jindi Kong, Jiaji He, Yiqiang Zhao, Yier Jin:
EMSim+: Accelerating Electromagnetic Security Evaluation with Generative Adversarial Network. 1-8 - Dengfeng Wang, Liukai Xu, Songyuan Liu, Zhi Li, Yiming Chen, Weifeng He, Xueqing Li, Yanan Sun:
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. 1-9 - Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski:
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method. 1-8 - Lóránt Meszlényi, Elif Bilge Kavun, Irem Keskinkurt Paksoy, Avesha Khalid, Tolga Yalçin:
Invited Paper: A Scalable Hardware/Software Co-Design Approach for Efficient Polynomial Multiplication. 1-5 - Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie:
Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators. 1-9 - Antonio Joia Neto, Adam Caulfield, Chistabelle Alvares, Ivan De Oliveira Nunes:
$\mathcal{D}\mathsf{iCA}$: A Hardware-Software Co-Design for Differential Check-Pointing in Intermittently Powered Devices. 1-9 - Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. 1-9 - Sanjay Gandham, Lingxiang Yin, Hao Zheng, Mingjie Lin:
SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload Balance. 1-9 - Jintao Li, Haochang Zhi, Weiwei Shan, Yongfu Li, Yanhan Zeng, Yun Li:
Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization. 1-9 - Xing Li, Lei Chen, Jiantang Zhang, Shuang Wen, Weihua Sheng, Yu Huang, Mingxuan Yuan:
EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning. 1-9 - Kuo-Wei Ho, Shao-Ting Chung, Tian-Fu Chen, Yu-Wei Fan, Che Cheng, Cheng-Han Liu, Jie-Hong R. Jiang:
WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits. 1-9 - Cheng Tan, Deepak Patil, Antonino Tumeo, Gabriel Weisz, Steven K. Reinhardt, Jeff Zhang:
VecPAC: A Vectorizable and Precision-Aware CGRA. 1-9 - Chen Chen, Vasudev Gohil, Rahul Kande, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran:
PSOFuzz: Fuzzing Processors with Particle Swarm Optimization. 1-9 - Lingjuan Wu, Hao Su, Xuelin Zhang, Yu Tai, Han Li, Wei Hu:
Automated Hardware Trojan Detection at LUT Using Explainable Graph Neural Networks. 1-9 - Sriram Ravula, Varun Gorti, Bo Deng, Swagato Chakraborty, James Pingenot, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, Alexandros G. Dimakis:
One-Dimensional Deep Image Prior for Curve Fitting of S-Parameters from Electromagnetic Solvers. 1-9 - Haibin Zhao, Priyanjana Pal, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori:
Power-Aware Training for Energy-Efficient Printed Neuromorphic Circuits. 1-9 - Chunxiao Lin, Muhammad Farhan Azmine, Yang Yi:
Invited Paper: Accelerating Next-G Wireless Communications with FPGA-Based AI Accelerators. 1-8 - Yinyi Liu, Bohan Hu, Zhenguo Liu, Peiyu Chen, Linfeng Du, Jiaqi Liu, Xianbin Li, Wei Zhang, Jiang Xu:
FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator. 1-9 - Bokyung Kim, Zhixu Du, Jingwei Sun, Yiran Chen:
Invited Paper: Towards the Efficiency, Heterogeneity, and Robustness of Edge AI. 1-7 - Ahmet Faruk Budak, Keren Zhu, David Z. Pan:
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. 1-8 - Irfansha Shaik, Jaco van de Pol:
Optimal Layout Synthesis for Quantum Circuits as Classical Planning. 1-9 - Jai-Ming Lin, Tsung-Chun Tsai, Rui-Ting Shen:
Routability-Driven Orientation-Aware Analytical Placement for System in Package. 1-8 - Marco Brohet, Felipe Valencia, Francesco Regazzoni:
Invited Paper: Instruction Set Extensions for Post-Quantum Cryptography. 1-6 - Ann Franchesca Laguna, Mohammad Mehdi Sharifi, Dayane Reis, Liu Liu, Andrew Hennessee, Clayton O'Dell, Ian O'Connor, Michael T. Niemier, X. Sharon Hu:
Invited Paper: Algorithm/Hardware Co-Design for Few-Shot Learning at the Edge. 1-9 - Hamza Errahmouni Barkam, Sanggeon Yun, Hanning Chen, Paul Gensler, Albi Mema, Andrew Ding, George Michelogiannakis, Hussam Amrouch, Mohsen Imani:
Reliable Hyperdimensional Reasoning on Unreliable Emerging Technologies. 1-9 - Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. 1-9 - Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang:
ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks. 1-9 - Fuyu Wang, Minghua Shen:
Automatic Kernel Generation for Large Language Models on Deep Learning Accelerators. 1-9 - Xin-Chuan Wu, Shavindra P. Premaratne, Kevin Rasch:
Invited Paper: Introduction to Hybrid Quantum-Classical Programming Using C++ Quantum Extension. 1-6 - Yifan Pan, Zichang He, Nanlin Guo, Zheng Zhang:
Distributionally Robust Circuit Design Optimization under Variation Shifts. 1-8 - Mingjie Liu, Haoyu Yang, Brucek Khailany, Haoxing Ren:
An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling. 1-9 - Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. 1-9 - Yonggan Fu, Yongan Zhang, Zhongzhi Yu, Sixu Li, Zhifan Ye, Chaojian Li, Cheng Wan, Yingyan Celine Lin:
GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models. 1-9 - Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, Hao Zheng:
ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects. 1-9 - Zhuolun He, Bei Yu:
Invited Paper: Heterogeneous Acceleration for Design Rule Checking. 1-7 - Haichuan Hu, Zichen Xu, Yuhao Wang, Fangming Liu:
Fast and Scalable Gate-Level Simulation in Massively Parallel Systems. 1-9 - Ziyang Yu, Chen Bai, Shoubo Hu, Ran Chen, Taohai He, Mingxuan Yuan, Bei Yu, Martin D. F. Wong:
IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration. 1-9 - Anjiang Wei, Akash Levy, Pu Yi, Robert M. Radway, Priyanka Raina, Subhasish Mitra, Sara Achour:
PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM. 1-9 - Haiyang He, Norman Chang, Jie Yang, Akhilesh Kumar, Wenbo Xia, Lang Lin, Rishikesh Ranade:
Invited Paper: Solving Fine-Grained Static 3DIC Thermal with ML Thermal Solver Enhanced with Decay Curve Characterization. 1-7 - Jianyong Yuan, Peiyu Wang, Junjie Ye, Mingxuan Yuan, Jianye Hao, Junchi Yan:
EasySO: Exploration-enhanced Reinforcement Learning for Logic Synthesis Sequence Optimization and a Comprehensive RL Environment. 1-9 - Ismail Bustany, Grigor Gasparyan, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang:
An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design. 1-9 - Arash Pashrashid, Ali Hajiabadi, Trevor E. Carlson:
HidFix: Efficient Mitigation of Cache-Based Spectre Attacks Through Hidden Rollbacks. 1-9 - Liying Yang, Guowei Sun, Hu Ding:
Towards Timing-Driven Routing: An Efficient Learning Based Geometric Approach. 1-9 - Hanqiu Chen, Hang Yang, Stephen B. R. Fitzmeyer, Cong Hao:
Rapid-INR: Storage Efficient CPU-Free DNN Training Using Implicit Neural Representation. 1-9 - Gaurav Kothari, Kanad Ghose:
Thermally-Aware Multi-Core Chiplet Stacking. 1-9 - Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong:
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. 1-9 - Shuzhang Zhong, Meng Li, Yun Liang, Runsheng Wang, Ru Huang:
Memory-aware Scheduling for Complex Wired Networks with Iterative Graph Optimization. 1-9 - Alessandro Tempia Calvino, Giovanni De Micheli:
Technology Mapping Using Multi-Output Library Cells. 1-9 - Yufei Chen, Xiao Dong, Wei-Kai Shih, Cheng Zhuo:
Invited Paper: Unleashing the Potential of Machine Learning: Harnessing the Dynamics of Supply Noise for Timing Sign-Off. 1-6
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