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2020 – today
- 2025
[j8]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(1): 200-213 (2025)- 2024
- [j7]Kaiqi Zhao
, Xiaochen Yuan, Tong Liu, Yan Xiang, Zhiyao Xie, Guoheng Huang, Li Feng:
CAMU-Net: Copy-move forgery detection utilizing coordinate attention and multi-scale feature fusion-based up-sampling. Expert Syst. Appl. 238(Part C): 121918 (2024) - [j6]Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Tunhou Zhang, Jiang Hu, Yiran Chen:
Toward Fully Automated Machine Learning for Routability Estimator Development. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 970-982 (2024) - [j5]Jian Peng, Tingyuan Liang, Jingbo Jiang, Yipu Zhang, Zhe Lin, Zhiyao Xie, Wei Zhang:
Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4753-4766 (2024) - [j4]Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang:
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. 17(3): 47:1-47:33 (2024) - [c29]Tao Zhang, Haoyu Yang, Kang Liu, Zhiyao Xie:
APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level. ASPDAC 2024: 374-379 - [c28]Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie:
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. ASPDAC 2024: 722-727 - [c27]Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. DAC 2024: 62:1-62:6 - [c26]Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang:
Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. DAC 2024: 183:1-183:6 - [c25]Yao Lu, Qijun Zhang, Zhiyao Xie:
Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies. ISLPED 2024: 1-6 - [i23]Mengming Li, Wenji Fang, Qijun Zhang, Zhiyao Xie:
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. CoRR abs/2401.13266 (2024) - [i22]Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie:
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR abs/2402.00386 (2024) - [i21]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR abs/2403.07257 (2024) - [i20]Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR abs/2403.18453 (2024) - [i19]Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang:
Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. CoRR abs/2404.08005 (2024) - [i18]Dimitrios Tsaras, Antoine Grosnit, Lei Chen, Zhiyao Xie, Haitham Bou-Ammar, Mingxuan Yuan:
ShortCircuit: AlphaZero-Driven Circuit Design. CoRR abs/2408.09858 (2024) - [i17]Qijun Zhang, Zhiyao Xie:
Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations. CoRR abs/2410.17782 (2024) - [i16]Qijun Zhang, Mengming Li, Yao lu, Zhiyao Xie:
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling. CoRR abs/2410.17789 (2024) - [i15]Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang:
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. CoRR abs/2411.14436 (2024) - 2023
- [j3]Kaiqi Zhao, Xiaochen Yuan, Zhiyao Xie, Yan Xiang, Guoheng Huang, Li Feng:
SPA-Net: A Deep Learning Approach Enhanced Using a Span-Partial Structure and Attention Mechanism for Image Copy-Move Forgery Detection. Sensors 23(14): 6430 (2023) - [j2]Zhiyao Xie, Jingyu Pan, Chen-Chia Chang, Jiang Hu, Yiran Chen:
The Dark Side: Security and Reliability Concerns in Machine Learning for EDA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1171-1184 (2023) - [c24]Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen:
Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. ASP-DAC 2023: 58-63 - [c23]Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, Yiran Chen:
Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. ASP-DAC 2023: 252-257 - [c22]Afzal Ahmad, Zhiyao Xie, Wei Zhang:
PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search. DAC 2023: 1-6 - [c21]Jian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang:
PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. DAC 2023: 1-6 - [c20]Fei Yan, Xiaodong Wang, Longfu Hong, Zhiyao Xie:
Deep Subspace K-Means Clustering for Syringe Defect Detection Without Defective Samples. DSIE 2023: 373-381 - [c19]Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang:
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. FPGA 2023: 15-25 - [c18]Zhiyao Xie, Xiaochen Yuan, Chan-Tong Lam, Guoheng Huang:
A Noise Convolution Network for Tampering Detection. ICANN (10) 2023: 38-48 - [c17]Kaiqi Zhao, Xiaochen Yuan, Zhiyao Xie, Guoheng Huang, Li Feng:
RA-Net: A Deep Learning Approach Based on Residual Structure and Attention Mechanism for Image Copy-Move Forgery Detection. ICANN (10) 2023: 371-381 - [c16]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. ICCAD 2023: 1-9 - [c15]Qijun Zhang, Shiyu Li, Guanglei Zhou, Jingyu Pan, Chen-Chia Chang, Yiran Chen, Zhiyao Xie:
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions. ICCAD 2023: 1-9 - [c14]Zhiyao Xie:
Efficient Runtime Power Modeling with On-Chip Power Meters. ISPD 2023: 168-174 - [c13]Zhiyao Xie, Tao Zhang, Yifeng Peng:
Security and Reliability Challenges in Machine Learning for EDA: Latest Advances. ISQED 2023: 1-6 - [i14]Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie:
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. CoRR abs/2308.05345 (2023) - [i13]Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. CoRR abs/2311.08441 (2023) - [i12]Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Yiran Chen:
EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. CoRR abs/2312.01674 (2023) - [i11]Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie:
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. CoRR abs/2312.08617 (2023) - [i10]Qijun Zhang, Shiyu Li, Guanglei Zhou, Jingyu Pan, Chen-Chia Chang, Yiran Chen, Zhiyao Xie:
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions. CoRR abs/2312.08994 (2023) - 2022
- [j1]Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Chen-Chia Chang, Jingyu Pan, Yiran Chen:
Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4667-4680 (2022) - [c12]Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen:
Towards collaborative intelligence: routability estimation based on decentralized private data. DAC 2022: 961-966 - [c11]Zhiyao Xie, Shiyu Li, Mingyuan Ma, Chen-Chia Chang, Jingyu Pan, Yiran Chen, Jiang Hu:
DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters. ICCAD 2022: 76:1-76:9 - [c10]Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, Yiran Chen:
Robustify ML-Based Lithography Hotspot Detectors. ICCAD 2022: 134:1-134:7 - [i9]Zhiyao Xie, Jingyu Pan, Chen-Chia Chang, Yiran Chen:
The Dark Side: Security Concerns in Machine Learning for EDA. CoRR abs/2203.10597 (2022) - [i8]Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen:
Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data. CoRR abs/2203.16009 (2022) - [i7]Zhiyao Xie:
Intelligent Circuit Design and Implementation with Machine Learning. CoRR abs/2206.03032 (2022) - [i6]Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang:
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. CoRR abs/2212.11582 (2022) - 2021
- [c9]Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen:
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. ASP-DAC 2021: 671-677 - [c8]Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen:
Automatic Routability Predictor Development Using Neural Architecture Search. ICCAD 2021: 1-9 - [c7]Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, Shidhartha Das:
APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. MICRO 2021: 1-14 - 2020
- [c6]Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen:
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. ASP-DAC 2020: 13-18 - [c5]Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza:
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. ASP-DAC 2020: 19-25 - [c4]Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen:
Fast IR Drop Estimation with Machine Learning : Invited Paper. ICCAD 2020: 13:1-13:8 - [c3]Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam:
Routing-Free Crosstalk Prediction. ICCAD 2020: 163:1-163:9 - [i5]Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen:
Fast IR Drop Estimation with Machine Learning. CoRR abs/2011.13491 (2020) - [i4]Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza:
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. CoRR abs/2011.13493 (2020) - [i3]Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen:
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. CoRR abs/2011.13494 (2020) - [i2]Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen:
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. CoRR abs/2011.13522 (2020) - [i1]Jingyu Pan, Chen-Chia Chang, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen:
Automatic Routability Predictor Development Using Neural Architecture Search. CoRR abs/2012.01737 (2020)
2010 – 2019
- 2019
- [c2]Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu:
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. DATE 2019: 180-185 - 2018
- [c1]Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Nvidia Corporation:
RouteNet: routability prediction for mixed-size designs using convolutional neural network. ICCAD 2018: 80
Coauthor Index
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