"Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing ..."

Wenji Fang et al. (2024)

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DOI: 10.48550/ARXIV.2403.18453

access: open

type: Informal or Other Publication

metadata version: 2024-04-10

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  - journals/corr/abs-2403-18453
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  - https://dblp.org/rec/journals/corr/abs-2403-18453
Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. CoRR abs/2403.18453 (2024)

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