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ORCID30th ASP-DAC 2025: Tokyo, Japan
- Yuichi Nakamura, Yu Wang:
Proceedings of the 30th Asia and South Pacific Design Automation Conference, ASPDAC 2025, Tokyo, Japan, January 20-23, 2025. ACM 2025, ISBN 979-8-4007-0635-6
System-Level Modeling and Design Methodologies
- Wujie Zhong
, Zijun Jiang, Yangdi Lyu:
MACO: A HW-Mapping Co-optimization Framework for DNN Accelerators. 1-7 - Zhiyao Li, Mingyu Gao:
KAPLA: Scalable NN Accelerator Dataflow Design Space Structuring and Fast Exploring. 8-15 - Arya Fayyazi, Mehdi Kamal, Massoud Pedram:
Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator Performance. 16-22 - Huidong Ji, Sheng Li, Yue Cao, Chen Ding, Jiawei Xu, Qitao Tan, Jun Liu, Ao Li, Xulong Tang, Lirong Zheng, Geng Yuan, Zhuo Zou:
A Computation and Energy Efficient Hardware Architecture for SSL Acceleration. 23-29
Tools and Techniques for On-Device AI Deployment
- Gurol Saglam, Florentia Afentaki, Georgios Zervakis, Mehdi B. Tahoori:
Sequential Printed Multilayer Perceptron Circuits for Super-TinyML Multi-Sensory Applications. 30-35 - Asmer Hamid Ali, Fan Zhang, Li Yang, Deliang Fan:
Learning to Prune and Low-Rank Adaptation for Compact Language Model Deployment. 36-42 - Zeqing Wang, Fei Cheng, Kangye Ji, Bohu Huang:
LightCL: Compact Continual Learning with Low Memory Footprint For Edge Device. 43-50 - Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu:
Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices. 51-57
AI and Logic Synthesis - A Perfect Match?
- Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Dino Ruic, Xiaoqing Xu:
High-Effort Logic Synthesis Using Randomized Transduction. 58-64 - Guande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi, Kang Zhao:
PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis. 65-71 - Faezeh Faez, Raika Karimi, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva:
MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization. 72-78
Application-Specific Computing-In-Memory
- Tsung-Yu Liu, Yen-An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng:
ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. 79-85 - Bing Li, Huaijun Liu, Yibo Du, Ying Wang:
High-Parallel In-Memory NTT Engine with Hierarchical Structure and Even-Odd Data Mapping. 86-92 - Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu:
Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning. 93-99 - Tianyi Yu, Tianyu Liao, Mufeng Zhou, Xiaotian Chu, Guodong Yin, Mingyen Lee, Yongpan Liu, Huazhong Yang, Xueqing Li:
DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level. 100-105
Machine Learning Based Physical Simulation and Physics-Aware Optimization
- Wenjian Yu, Shan Shen, Dingcheng Yang, Haoyuan Li, Jiechen Huang, Chunyan Pei:
Deep Learning Inspired Capacitance Extraction Techniques. 106-112 - Xinling Yu, Ziyue Liu, Hai Li, Ian A. Young, Zheng Zhang:
Enhanced Operator Learning for Scalable and Ultra-fast Thermal Simulation in 3D-IC Design. 113 - Jiqing Jiang, Yongqiang Duan, Zhou Jin:
Boosting the Performance of Transistor-Level Circuit Simulation with GNN. 114-120 - Garth Sundberg, Rodger Luo:
Emag-Aware ML-Based Layout Optimization for High-Speed IC Design. 121-127
CEDA/CASS/SSCS Joint Session on Silicon Photonics
- Zahra Ghanaatian, Asif Mirza, Amin Shafiee, Sudeep Pasricha, Mahdi Nikdast:
Invited paper: Bridging EDA and Silicon Photonics Design: Enabling Robust-by-Design Photonic Integrated Circuits. 128-134 - Yuxiang Fu, Yinyi Liu, Ngai Wong, Jiang Xu:
Invited paper: SPICE-Compatible Modeling and Design for Electronic-Photonic Integrated Circuits. 135-140 - Jaeha Kim:
Invited paper: Modeling and Simulation of Silicon Photonics Systems in SystemVerilog/XMODEL. 141-146 - Woo-Young Choi, Dae-Won Rho, Jae-Koo Park, Seung-Jae Yang, Jae-Ho Lee, Yongjin Ji:
Invited paper: Si Photonic Ring-Resonator-Based WDM Transceivers. 147
Accelerating Vision and Transformer Models
- Li Ding, Jun Liu, Shan Huang, Guohao Dai:
ViDA: Video Diffusion Transformer Acceleration with Differential Approximation and Adaptive Dataflow. 148-154 - Qichu Sun, Rui Meng, Haishuang Fan, Fangqiang Ding, Linxi Lu, Jingya Wu, Xiaowei Li, Guihai Yan:
APTO: Accelerating Serialization-Based Point Cloud Transformers with Position-Aware Pruning. 155-162 - Kairui Sun, Meiqi Wang, Junhai Zhou, Zhongfeng Wang:
UEDA: A Universal And Efficient Deformable Attention Accelerator For Various Vision Tasks. 163-169 - Hao Zhou, Yang Liu, Hongji Wang, Enhao Tang, Shun Li, Yifan Zhang, Guohao Dai, Yongpan Liu, Kun Wang:
Deploying Diffusion Models with Scheduling Space Search and Memory Overflow Prevention Based on Graph Optimization. 170-176 - Guang Yang, Xinming Yan, Hui Kou, Zihan Zou, Qingwen Wei, Hao Cai, Bo Liu:
TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment. 177-182
Shaping the Future of Analog EDA
- Baiyu Chen, Jiawen Cheng, Wenjian Yu:
A Practical Randomized GMRES Algorithm for Solving Linear Equation System in Circuit Simulation. 183-189 - Jintao Li, Haochang Zhi, Jiang Xiao, Yanhan Zeng, Weiwei Shan, Yun Li:
Balancing Objective Optimization and Constraint Satisfaction for Robust Analog Circuit Optimization. 190-196 - Haochang Zhi, Jintao Li, Yun Li, Weiwei Shan:
Analog Circuit Transfer Method Across Technology Nodes via Transistor Behavior. 197-203 - Lijie Wang, Jing Wang, Song Chen, Qi Xu:
AIPlace: Analog IC Placement with Multi-Task Learning Framework. 204-210
Approximate and Stochastic Computing
- Xincheng Feng, Guodong Shen, Jianhao Hu, Meng Li, Ngai Wong:
Stochastic Multivariate Universal-Radix Finite-State Machine: a Theoretically and Practically Elegant Nonlinear Function Approximator. 211-217 - Zhongyu Guan, Qiang Liu, Guangdong Lin:
ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point Multiplier. 218-223 - Lan-yang Sun, Yaoru Hou, Hao Cai:
AmPEC: Approximate MRAM with Partial Error Correction for Fine-grained Energy-quality Trade-off. 224-229 - Lakshmi Sai Niharika Vulchi, Pranathi Valipireddy, Mahati Basavaraju, Madhav Rao:
HyPPO: Hybrid Piece-wise Polynomial Approximation and Optimization for Hardware Efficient Designs. 230-236 - Maliha Tasnim, Sachin Sachdeva, Yibo Liu, Sheldon X.-D. Tan:
Hybrid Temporal Computing for Lower Power Hardware Accelerators. 237-244
Next-Generation Embedded Architectures and Tools
- Huai-De Peng, Yi-Shen Chen, Tseng-Yi Chen, Yuan-Hao Chang:
PULSE: Progressive Utilization of Log-Structured Techniques to Ease SSD Write Amplification in B-epsilon-tree. 245-250 - Hui-Tang Luo, Tseng-Yi Chen:
Rethinking B-epsilon tree Indexing Structure over NVM with the Support of Multi-write Modes. 251-257 - Kai Qian, Haodong Lu, Yinqiu Liu, Zexu Zhang, Kun Wang:
End-to-end Compilation is All FPGAs Need: A Unified Overlay-based FPGA Compiler for Deep Learning. 258-264 - Shangli Li, Mingjie Xing, Yanjun Wu:
HDCC: A Hierarchical Dataflow-Oriented CGRA Compiler for Complex Applications. 265-271 - Qilin Si, Benjamin Carrión Schäfer:
HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAs. 272-278
Advances in 3D-IC and Ultra-Large-Scale Integration
- Zhen Zhuang, Quan Chen, Hao Yu, Tsung-Yi Ho:
Fast Routing Algorithm for Mask Stitching Region of Ultra Large Wafer Scale Integration. 279-284 - Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu:
The Survey of 2.5D Integrated Architecture: An EDA perspective. 285-293 - Xueyan Zhao, Weiguo Li, Zhisheng Zeng, Zhipeng Huang, Biwei Xie, Xingquan Li, Yungang Bao:
Toward Advancing 3D-ICs Physical Design: Challenges and Opportunities. 294-301 - Miao Liu, Qingqing Sun, David Wei Zhang:
Processing-Near-Memory with Chip Level 3D-IC. 302-307 - Gyumin Kim, Heechun Park:
Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs. 308-314
University Design Contest
- Yifan Qin, Zhenge Jia, Zheyu Yan, Jay Mok, Manto Yung, Yu Liu, Xuejiao Liu, Wujie Wen, Luhong Liang, Kwang-Ting Tim Cheng, Xiaobo Sharon Hu, Yiyu Shi:
A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection. 315-316 - Zhiwei Zhong, Yijie Wei, Lance Christopher Go, Yiqi Li, Jie Gu:
Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR Applications. 317-320 - Qiankai Cao, Yiqi Li, Juin Chuen Oh, Jie Gu:
Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse Kinematics. 321-324 - Yuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge:
A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. 325-327 - Heming Sun, Jing Wang, Silu Liu, Shinji Kimura, Masahiro Fujita:
Learned Image Codec on FPGA: Algorithm, Architecture and System Design. 328-331 - Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi:
Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices. 332-334 - Yichao Ji, Ji Jin, Lin Cheng:
A High-Density Hybrid Buck Converter with a Charge Converging Phase Reducing Inductor Current for 12V Power Supply Systems. 335-337 - Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han:
A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology. 338-341 - Yi Zhang, Minzhe Tang, Zheng Li, Dongfan Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada:
A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate. 342-343 - Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka:
Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection. 344-347 - Koji Kikuta, Takashi Hisakado, Mahfuzul Islam:
Self-recovery hysteresis control based on-chip SC DC-DC converter robust to load fluctuation. 348-351 - Dongfan Xu, Minzhe Tang, Yi Zhang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada:
A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NR. 352-353 - Chenxin Liu, Zheng Li, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Shinsuke Hara, Akifumi Kasamatsu, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada:
A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO. 354-355 - Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose:
Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devices. 356-359 - Sota Kano, Naoto Usami, Atsushi Tomiki, Tetsuya Iizuka:
Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes. 360-363 - Hiroaki Kitaike, Hironori Tagawa, Shufan Xu, Ruilin Zhang, Kunyang Liu, Kiichi Niitsu:
Design of 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording. 364-367 - Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose:
Ultra Low-power Capacitively-coupled Chopper Amplifier Focusing on the Sparsity of Compressed Sensing for EEG Recording. 368-371
LLM Acceleration and Specialization for Circuit Design and Edge Applications
- Chung-Kuan Cheng, Byeonggon Kang, Bill Lin, Yucheng Wang:
Standard Cell Layout Generation: Review, Challenges, and Future Works. 372-378 - Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi:
ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges. 379-384 - Zhengrui Chen, Chengjun Guo, Zixuan Song, Guozhu Feng, Shizhang Wang, Li Zhang, Xunzhao Yin, Zhenhua Wu, Zheyu Yan, Cheng Zhuo:
Invited Paper: Boosting Standard Cell Library Characterization with Machine Learning. 385-391 - Kairong Guo, Xiaohan Gao, Haoyi Zhang, Runsheng Wang, Ru Huang, Yibo Lin:
Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells. 392
Timing Analysis and Optimization
- Fahad Rahman Amik, Yousef Safari, Zhanguang Zhang, Boris Vaisband:
Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model. 393-400 - Yushan Wang, Xu He, Renjun Zhao, Yao Wang, Chang Liu, Yang Guo:
SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner Consideration. 401-406 - Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang:
iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis. 407-415 - Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang:
PathGen: An Efficient Parallel Critical Path Generation Algorithm. 416-424 - Kaixiang Zhu, Wai-Shing Luk, Lingli Wang:
Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value Distribution. 425-432
Side Channel Attacks and Trusted Execution Environment
- Md. Imtiaz Rashid, Benjamin Carrión Schäfer:
Making Legacy Hardware Robust against Side Channel Attacks via High-Level Synthesis. 433-439 - Nan Wang, Ruichao Liu, Yufeng Shan, Yu Zhu, Song Chen:
Machine Learning-Based Real-Time Detection of Power Analysis Attacks Using Supply Voltage Comparisons. 440-446 - Brojogopal Sapui, Mehdi B. Tahoori:
Side-channel Collision Attacks on Hyper-Dimensional Computing based on Emerging Resistive Memories. 447-453 - Shangjie Pan, Xuanyao Peng, Zeyuan Man, Xiquan Zhao, Dongrong Zhang, Bicheng Yang, Dong Du, Hang Lu, Yubin Xia, Xiaowei Li:
Dep-TEE: Decoupled Memory Protection for Secure and Scalable Inter-enclave Communication on RISC-V. 454-460 - Hassan Nassar, Jeferson González-Gómez, Varun Manjunath, Lars Bauer, Jörg Henkel:
Through Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC Systems. 461-467
Frameworks and Modeling for Computing-In-Memory
- Zichen Qian, Rentao Wan, Chin-Hsiang Liao, Steven Koester, Mingoo Seok:
Theoretical Optimal Specifications of Memcapacitors for Charge-Based In-Memory Computing. 468-475 - Umar Afzaal, Seunggyu Lee, Youngsoo Shin:
An Island Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided Logic. 476-482 - Dongin Lee, Enhyeok Jang, Seungwoo Choi, Junwoong An, Cheolhwan Kim, Won Woo Ro:
PIMutation: Exploring the Potential of Real PIM Architecture for Quantum Circuit Simulation. 483-490 - Zikang Xu, Yiming Zhang, Zhirong Shen:
A Fail-Slow Detection Framework for HBM Devices. 491-497
AI/ML for Circuit Design and Prediction
- Sadaf Khan, Zhengyuan Shi, Ziyang Zheng, Min Li, Qiang Xu:
DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations. 498-504 - Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. 505-512 - Jongho Yoon, Jakang Lee, Donggyu Kim, Junseok Hur, Seokhyeong Kang:
ParaFormer: A Hybrid Graph Neural Network and Transformer Approach for Pre-Routing Parasitic RC Prediction. 513-519 - Lizi Zhang, Azadeh Davoodi:
Static IR Drop Prediction with Limited Data from Real Designs. 520-526 - Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie:
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. 527-533
Advanced Methods in AI Hardware Co-Design
- Jiaming Xu, Jinhao Li, Jun Liu, Hao Zhou, Guohao Dai:
Accelerator for LLM-Enhanced GNN with Product Quantization and Unified Indexing. 534-540 - Cong Wang, Zeming Chen, Shanshi Huang:
MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator. 541-547 - Haojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin:
DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures. 548-553 - Leran Huang, Yongpan Liu, Xinyuan Lin, Chenhan Wei, Wenyu Sun, Zengwei Wang, Boran Cao, Chi Zhang, Xiaoxia Fu, Wentao Zhao, Sheng Zhang:
MPICC: Multiple-Precision Inter-Combined MAC Unit with Stochastic Rounding for Ultra-Low-Precision Training. 554-559
Communication Networks
- Wei-Yao Kao, Tai-Jung Lin, Yao-Wen Chang:
Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based Models. 560-566 - Shibo Chen, Hailun Zhang, Todd M. Austin:
Zipper: Latency-Tolerant Optimizations for High-Performance Buses. 567-574 - Zixuan Liu, Yaoyao Ye:
A Buffer Reservation Scheduling Strategy for Enhancing Performance of NoC Router Bypassing. 575-580 - Xinghao Zhu, Jiyuan Bai, Zifeng Zhao, Qirong Yu, Xiaofang Zhou, Gengsheng Chen:
RUNoC: Re-inject into the Underground Network to Alleviate Congestion in Large-Scale NoC. 581-586
Design and Optimization of Emerging Embedded Applications
- Limin Jiang, Yi Shi, Yintao Liu, Qingyu Deng, Siyi Xu, Yihao Shen, Fangfang Ye, Shan Cao, Zhiyuan Jiang:
A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing. 587-593 - Fangxin Liu, Zongwu Wang, Peng Xu, Shiyuan Huang, Li Jiang:
Exploiting Differential-Based Data Encoding for Enhanced Query Efficiency. 594-600 - Huan-Chun Yeh, Yu-Zheng Su, Chun-Han Lin:
Automated Power-saving User-interfaces for Application Designers. 601-606 - Chun-Hsian Huang, Zhi-Rui Chen, Huai-Shu Hsu:
An Edge AI and Adaptive Embedded System Design for Agricultural Robotics Applications. 607-613
Verification and Testing in Machine Lerning Era
- Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang:
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. 614-621 - Thai-Hoang Nguyen, Youngjin Ju, Dongsub Yoon, Hyojin Choi:
Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural Networks. 622-627 - Yun-Feng Yang, Wei-Shen Wang, Yung-Jen Lee, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li, Jessica Yen, Lang Lin:
Efficient ML-Based Transient Thermal Prediction for 3D-ICs. 628-634 - Sicong Yuan, Changhao Wang, Moritz Fieback, Hanzhi Xun, Mottaqiallah Taouil, Xiuyan Li, Danyang Chen, Lin Wang, Nicolò Bellarmino, Riccardo Cantoro, Said Hamdioui:
Device-Aware Test for Anomalous Charge Trapping in FeFETs. 635-641
Hybrid/Co-Designed Near/In Memory Computing
- Yiming Chen, Xirui Du, Guodong Yin, Wenjun Tang, Yongpan Liu, Huazhong Yang, Xueqing Li:
3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro. 642-647 - Shubham Negi, Utkarsh Saxena, Deepika Sharma, Kaushik Roy:
HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads. 648-655 - Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing. 656-662 - Yitong Zhou, Wente Yi, Sifan Sun, Wenjia Wang, Jinyu Bai, He Zhang, Wang Kang:
A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation Strategies. 663-668
ML for IC Design and Manufacturing: When Is It Real?
- Amur Ghose, Andrew B. Kahng, Sayak Kundu, Yiting Liu, Bodhisatta Pramanik, Zhiang Wang, Dooseok Yoon:
Use Cases and Deployment of ML in IC Physical Design. 669-675 - Jinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, Seonghyeon Park, Jaemin Seo, Jongho Yoon, Seokhyeong Kang:
Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement. 676-682 - Hyunsu Chae, Song Hang Chai, Taiyun Chi, Sensen Li, David Z. Pan:
ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA. 683-689 - Youngsoo Shin:
ML for Computational Lithography: Practical Recipes. 690-692
Innovations in Deep Learning and Neural Network Acceleration
- Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu:
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference. 693-699 - Xilong Kang, Qingwen Wei, Ningyuan Li, Xingyu Xu, Hao Cai, Bo Liu:
SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device. 700-705 - Marco Ronzani, Cristina Silvano:
FactorFlow: Mapping GEMMs on Spatial Architectures through Adaptive Programming and Greedy Optimization. 706-712 - Yanyue Xie, Zhengang Li, Dana Diaconu, Suranga Handagala, Miriam Leeser, Xue Lin:
LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference. 713-719 - Haoxiang Zhou, Zikun Wei, Dingbang Liu, Liuyang Zhang, Chenchen Ding, Jiaqi Yang, Wei Mao, Hao Yu:
A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs. 720-726
Neuromorphic and Emerging Computing Techniques
- Yitian Zhou, Yue Li, Yang Hong:
HyCOMP: A Compiler for ANN-SNN Hybrid Accelerators. 727-733 - Haomin Li, Fangxin Liu, Zewen Sun, Zongwu Wang, Shiyuan Huang, Ning Yang, Li Jiang:
NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks. 734-740 - Bo Li, Yue Liu, Wei Liu, Jinghai Wang, Xiao Huang, Zhiyi Yu, Shanlin Xiao:
SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks. 741-747 - Jiaqi Liu, Yiwen Ma:
OpticalHDC: Ultra-fast Photonic Hyperdimensional Computing Accelerator. 748-753 - Paula Carolina Lozano Duarte, Florentia Afentaki, Georgios Zervakis, Mehdi B. Tahoori:
Design and In-training Optimization of Binary Search ADC for Flexible Classifiers. 754-760
Package and PCB
- Yi-Sian Ciou, Ying-Jie Jiang, Yi-Yu Liu, Shao-Yun Fang, Wen-Hao Liu:
Paired-Spacing-Constrained Package Routing with Net Ordering Optimization. 761-767 - Ding-Hsun Lin, Tsubasa Koyama, Yu-Jen Chen, Keng-Tuan Chang, Chih-Yi Huang, Chen-Chao Wang, Tsung-Yi Ho:
Hybrid Detour Refinement Strategy for Package Substrate Routing. 768-773 - Hao-Ju Chang, Yu-Hung Chen, Hao-Wei Huang, Yihua Yeh, Hung-Ming Chen, Chien-Nan Jimmy Liu:
On Awareness of Offset-Via and Teardrop in Advanced Packaging Interconnect Synthesis. 774-780 - Lin Chen, Ran Chen, Shoubo Hu, Xufeng Yao, Zhentao Tang, Shixiong Kai, Siyuan Xu, Mingxuan Yuan, Jianye Hao, Bei Yu, Jiang Xu:
PCBAgent: An Agent-based Framework for High-Density Printed Circuit Board Placement. 781-787
Logic Locking and Hardware Watermarking
- Md. Saad Ul Haque, Azim Uddin, Jingbo Zhou, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor:
NoXLock: SiP Activation and Licensing through Obfuscated on-Chip Network and Fuzzy Traffic. 788-793 - Kevin Lopez, Amin Rezaei:
K-Gate Lock: Multi-Key Logic Locking Using Input Encoding Against Oracle-Guided Attacks. 794-800 - Dipali Deepak Jain, Guangwei Zhao, Rajesh Kumar Datta, Kaveh Shamsi:
A Hybrid Machine Learning and Numeric Optimization Approach to Analog Circuit Deobfuscation. 801-807 - Kun Wang, Kaiyan Chang, Mengdi Wang, Xingqi Zou, Haobo Xu, Yinhe Han, Ying Wang:
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. 808-813
AI-Driven Innovative Design Methods
- Jaeseung Lee, Sunggyu Jang, Jakang Lee, Seokhyeong Kang:
LIBMixer: An all-MLP Architecture for Cell Library Characterization towards Design Space Optimization. 814-820 - Lichao Zeng, Zhouzhouzhou Mei, Zhongyu Shi, Yining Chen:
DefectTrackNet: Efficient Root Cause Analysis of Wafer Defects in Semiconductor Manufacturing Using a Lightweight CNN-Transformer Architecture. 821-827 - Jinyoung Choi, HyunJoon Jeong, Jeong-Taek Kong, Soyoung Kim:
Hybrid Compact Modeling Strategy: A Fully-Automated and Accurate Compact Model with Physical Consistency. 828-834 - Qinghang Zhao, Tao Li:
CAR-Net: Solving Electrical Crosstalk Problem in Capacitive Sensing Array. 835-841 - Youngchang Choi, Sejin Park, Ho-Jin Lee, Kyongsu Lee, Jae-Yoon Sim, Seokhyeong Kang:
PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog Circuits. 842-848
Beyond Digital: Advancing Design Automation for Physical Computing Systems
- Suma George Cardwell, J. Darby Smith, Karan Patel, Andrew Maicke, Jared Arzate, Samuel Liu, Jaesuk Kwon, Christopher Allemang, Douglas Cale Crowder, Shashank Misra, Frances S. Chance, Catherine D. Schuman, Jean Anne C. Incorvia, James Bradley Aimone:
AI-Guided Codesign for Novel Computing Paradigms. 849-856 - Sara Achour:
Towards Design Optimization of Analog Compute Systems. 857-864 - Chuan Liu, Chunshu Wu, Ruibing Song, Yousu Chen, Ang Li, Michael C. Huang, Tony Tong Geng:
Nature-GL: A Revolutionary Learning Paradigm Unleashing Nature's Power in Real-World Spatial-Temporal Graph Learning. 865-871 - Nicolas Bohm Agostini, Connah Johnson, William Cannon, Antonino Tumeo:
ChemComp: A Compilation Framework for Computing with Chemical Reaction Networks. 872-878
Floorplan and Placement
- Eunsol Jeong, Taewhan Kim, Heechun Park:
PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. 879-885 - Zirui Li, Kanglin Tian, Jianwang Zhai, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao:
FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs. 886-892 - Cheng-Yu Chiang, Yi-Hsien Chiang, Chao-Chi Lan, Yang Hsu, Che-Ming Chang, Shao-Chi Huang, Sheng-Hua Wang, Yao-Wen Chang, Hung-Ming Chen:
Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization. 893-899 - Xinfei Liu, Siting Liu, Bei Yu, Song Chen, Qi Xu:
ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator. 900-906 - Zewen Li, Ke Tang, Lang Feng, Zhongfeng Wang:
An MIP-based Force-directed Large Scale Placement Refinement Algorithm. 907-913
Let's Quantumize: Welcome to the World of Quantum
- Armin Abdollahi, Mehdi Kamal, Massoud Pedram:
ICD2S: A Hybrid Ising-Classical-Machines Data-Driven QUBO Solver Method. 914-920 - Daniel Bochen Tan, Wan-Hsuan Lin, Jason Cong:
Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling. 921-929 - Mingfei Yu, Alessandro Tempia Calvino, Mathias Soeken, Giovanni De Micheli:
Back-end-aware Fault-tolerant Quantum Oracle Synthesis. 930-937
Innovative Techniques for Energy-Efficient and Reliable Hardware Systems
- Haijin Su, Xin Hong, Maimaiti Nazhamaiti, Ce Zhang, Li Luo, Qi Wei, Zheyu Liu, Wenjie Deng, Yongzhe Zhang, Fei Qiao:
FEI: Fusion Processing of Sensing Energy and Information for Self-Sustainable Infrared Smart Vision System. 938-944 - Seoyoon Jang, Sangouk Jeon, Kwanghyun Shin, Dongkwon Lee, Hankyu Chi, Wookjin Shin, Changhyun Pyo, Jaeha Kim, Dongsuk Jeon:
WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory. 945-951 - Tong Cheng, Zirui Xu, Xinyi Li, Li Li, Yuxiang Fu:
Compact Interleaved Thermal Control for Improving Throughput and Reliability of Networks-on-Chip. 952-958 - Le Zhang, Onat Güngör, Flavio Ponzina, Tajana Rosing:
E-QUARTIC: Energy Efficient Edge Ensemble of Convolutional Neural Networks for Resource-Optimized Learning. 959-965 - Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto:
Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications. 966-973
Leveraging Large Language Models in Hardware Design
- Shan Huang, Jinhao Li, Zhen Yu, Jiancai Ye, Jiaming Xu, Ningyi Xu, Guohao Dai:
LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration. 974-980 - Kimia Tasnia, Sazadur Rahman:
OPL4GPT: An Application Space Exploration of Optimal Programming Language for Hardware Design by LLM. 981-987 - Jiahao Gai, Hao Chen, Zhican Wang, Hongyu Zhou, Wanru Zhao, Nicholas D. Lane, Hongxiang Fan:
Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis. 988-994 - Manar Abdelatty, Jingxiao Ma, Sherief Reda:
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs. 995-1001 - Mohammad Akyash, Hadi Mardani Kamali:
SimEval: Investigating the Similarity Obstacle in LLM-based Hardware Code Generation. 1002-1007
Accelerator Design Methodologies
- You-Kai Zheng, Ming-Liang Wei, Hsiang-Yun Cheng, Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong, Po-Hao Tseng, Hsiang-Pang Li:
In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis. 1008-1015 - Ankur Limaye, Nicolas Bohm Agostini, Claudio Barone, Vito Giovanni Castellana, Michele Fiorito, Fabrizio Ferrandi, Andres Marquez, Antonino Tumeo:
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems. 1016-1022 - Yuan Dai, Xuchen Gao, Chen Shen, Bingbing Peng, Wenbo Yin, Wai-Shing Luk, Lingli Wang:
Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring. 1023-1030 - Wan-Luan Lee, Dian-Lun Lin, Cheng-Hsiang Chiu, Ulf Schlichtmann, Tsung-Wei Huang:
HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner. 1031-1040
Advanced Architectures for Scientific and Edge Computing
- Cong Hao:
Exploring and Exploiting Runtime Reconfigurable Floating Point Precision in Scientific Computing: a Case Study for Solving PDEs. 1041-1047 - Jiadong Zhu, Dongsheng Zuo, Yuzhe Ma:
A Holistic FPGA Architecture Exploration Framework for Deep Learning Acceleration. 1048-1054 - Xiaoling Yi, Ryan Antonio, Joren Dumoulin, Jiacong Sun, Josse Van Delm, Guilherme Pereira Paim, Marian Verhelst:
OpenGeMM: A Highly-Efficient GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling. 1055-1061 - Qijun Zhang, Zhiyao Xie:
Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations. 1062-1069
The Science of Light: The New Advancement of Photonic Computing
- Sijie Fei, Amro Eldebiky, Grace Li Zhang, Bing Li, Ulf Schlichtmann:
An Efficient General-Purpose Optical Accelerator for Neural Networks. 1070-1076 - Ziyang Jiang, Pingchuan Ma, Meng Zhang, Z. Rena Huang, Jiaqi Gu:
ADEPT-Z: Zero-Shot Automated Circuit Topology Search for Pareto-Optimal Photonic Tensor Cores. 1077-1083 - Bo Xu, Yuetong Fang, Shaoliang Yu, Renjing Xu:
Reuse and Blend: A Weight-Sharing Energy-Efficient Optical Neural Network. 1084-1090 - Jiaqi Liu, Xianbin Li:
PhotonGraph: High-performance Photonic Graph Processing Accelerator. 1091-1096
From Math to Circuits
- Bhavani Sampathkumar, Ritaja Das, Bailey Martin, Florian Enescu, Priyank Kalla:
An Algebraic Approach to Partial Synthesis of Arithmetic Circuits. 1097-1103 - Paul Teng, Christophe Dubach:
Hardware Synthesizable Exceptions using Continuations. 1104-1111 - Andrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli:
Area-Oriented Optimization After Standard-Cell Mapping. 1112-1119
Innovative Techniques in AI Model Optimization and Training
- Yan Wang, Xingbin Wang, Yulan Su, Sisi Zhang, Zechao Lin, Dan Meng, Rui Hou:
ROBIN: A Novel Framework for Accelerating Robust Multi-Variant Training. 1120-1125 - Binyi Fang, Yixin Yang, Jingjing Chang, Ziyang Gao, Hai-Bao Chen:
Dual-branch cross-modal fusion with local-to-global learning for UAV object detection. 1126-1132 - Yiwei Zhao, Jinhui Chen, Sai Qian Zhang, Syed Shakib Sarwar, Kleber Hugo Stangherlin, Jorge Tomás Gómez, Jae-Sun Seo, Barbara De Salvo, Chiao Liu, Phillip B. Gibbons, Ziyun Li:
H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications. 1133-1141
Rapidus' Initiatives to Half Semiconductor Development Time
- Koki Tsurusaki:
Raads: Rapidus's AI/ML based assisted design flow to reduce design period halved. 1142 - Masaharu Kobayashi:
DMCO: A Strategy for Design-Manufacturing Co-optimization. 1143 - Hideki Sasaki:
Advanced Packaging Technology and Design Methodology for Next Generation Chiplets. 1144
System Level Modelling & Optimization
- Qijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie:
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling. 1145-1152 - Dingcui Yu, Longfei Luo, Han Wang, Yina Lv, Liang Shi:
DISS: A Novel Data Invalidation Scheme for Swap-Data on Flash Storage Systems. 1153-1159 - Khalil Esper, Stefan Wildermann, Jürgen Teich:
Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs. 1160-1166 - Zheng Wu, Jinyi Shen, Xuyang Zhao, Changxu Liu, Li Shang, Fan Yang:
TL-CSE: Microarchitecture-Compiler Co-design Space Exploration via Transfer Learning. 1167-1173
Emerging Trends in Reconfigurable and Compute-in-Memory
- Gunil Kang, Dahoon Park, Hojin Lee, Sangwoo Jung, Jiyong Park, Jung Gyu Min, Youngjoo Lee, Jaeha Kung:
RISC-V Driven Orchestration of Vector Processing Units and eFlash Compute-in-Memory Arrays for Fast and Accurate Keyword Spotting. 1174-1180 - Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang:
Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor Cores. 1181-1187 - Thinh NguyenQuang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki:
Large-Scale AGV Routing Based on Multi-FPGA SQA Acceleration. 1188-1194 - Pol Puigdemont, Enrico Russo, Axel Wassington, Abhijit Das, Sergi Abadal, Maurizio Palesi:
A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference. 1195-1201
Adaptive and Flexible Memory Architecture
- Junfei Liu, Anson Kahng:
FPBA: Flexible Percentile-Based Allocation for Multiple-Bits-Per-Cell RRAM. 1202-1208 - Mengyue Xi, Tianyu Guo, Xuanteng Huang, Zejia Lin, Xianwei Zhang:
Mpache: Interaction Aware Multi-level Cache Bypassing on GPUs. 1209-1215 - Cheng-Yen Lee, Sunil P. Khatri, Ali Ghrayeb:
A Novel Mixed-Signal Flash-based Finite Impulse Response (FFIR) Filter for IoT Applications. 1216-1222 - Xing Wang, Tianhui Jiao, Shaochen Li, Yuchen Ma, Zhican Zhang, Zhichao Liu, Xi Chen, Xin Si:
TRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-Tree. 1223-1229
Reliability in Physical Design
- Yichen Cai, Linyu Zhu, Xinfei Guo:
Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing Awareness. 1230-1236 - Man-Ling Hong, Ying-Jie Jiang, Shao-Yun Fang:
Pin Access-aware Multiple Via Pillar Co-Design for Routability Optimization. 1237-1242 - Jiun-Cheng Tsai, Hsuan-Ming Huang, Wei-Min Hsu, Pei-Ting Lee, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, Charles H.-P. Wen:
ResCap: Fast-yet-Accurate Capacitance Extraction for Standard Cell Design by Physics-Guided Machine Learning. 1243-1250 - Yan-Ting Chen, Zhidan Zheng, Shao-Yun Fang, Tsun-Ming Tseng, Ulf Schlichtmann:
CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip. 1251-1256
Hardware Authenticity Towards a Trustworthy Society
- Takahiro Ishikawa, Kose Yokooji, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani, Jun Shiomi:
Hardware Trojan Detection by Fine-grained Power Domain Partitioning. 1257-1263 - Ayano Takaya, Ryuichi Nakajima, Jun Shiomi, Michihiro Shintani:
Cryo-HT: Hardware Trojan Activated at Cryogenic Temperatures. 1264-1269 - Daisuke Fujimoto, Yuichi Hayashi:
Current consumption model for more efficient side-channel tolerant design at FPGA design stage. 1270-1274 - Leon Li, Alex Orailoglu:
White-box logic obfuscation: A Transparent Solution to Hardware Piracy and Reverse Engineering. 1275-1281
Homomorphic Encryption and Cloud Security
- Chaitali Sathe, Yiorgos Makris, Benjamin Carrión Schäfer:
Efficient and Secure Cloud-based Split Logic Synthesis. 1282-1287 - Seoyoon Jang, Sungjin Park, Dongsuk Jeon:
Efficient Key Switching Accelerator for Fully Homomorphic Encryption. 1288-1294 - Haotian Lu, Ziang Yin, Partho Bhoumik, Sanmitra Banerjee, Krishnendu Chakrabarty, Jiaqi Gu:
The Unlikely Hero: Nonidealities in Analog Photonic Neural Networks as Built-in Adversarial Defenders. 1295-1301 - Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang:
Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data. 1302-1307 - Chen-Chia Chang, Wan-Hsuan Lin, Jingyu Pan, Guanglei Zhou, Zhiyao Xie, Jiang Hu, Yiran Chen:
PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection. 1308-1313
Advanced Modeling, Simulation, and Verification
- Jiahao Xu, Chunyan Pei, Shengbo Tong, Wenjian Yu:
Efficient Hypergraph Modeling of VLSI Circuits for the MFS-Based Emulation and Simulation Acceleration. 1314-1320 - Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li:
ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. 1321-1327 - Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek:
DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits. 1328-1335 - Zijian Jiang, Keran Zheng, David Boland, Yungang Bao, Kan Shi:
Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration. 1336-1342 - Sourav Das, Aritra Hazra, Pallab Dasgupta, Himanshu Jain, Sudipta Kundu:
SISCO: Selective Invariant Sharing, Clustering and Ordering for Effective Multi-Property Formal Verification. 1343-1349
Carbon, Light, Fluids: Emerging Technologies
- Shinobu Miwa, Eiichiro Sekikawa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda:
CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors. 1350-1356 - Yushen Zhang, Dragan Raseta, Tsun-Ming Tseng, Ulf Schlichtmann:
3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control. 1357-1363 - Meng Lian, Shucheng Yang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
Dynamic Topology-Aware Flow Path Construction and Scheduling Optimization for Multilayered Continuous-Flow Microfluidic Biochips. 1364-1371 - Zhidan Zheng, You-Jen Chang, Liaoyuan Cheng, Tsun-Ming Tseng, Ulf Schlichtmann:
A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip Topologies. 1372-1378 - Yiyang Sun, Peiran Yan, Yiqi Jing, Le Ye, Tianyu Jia:
GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization. 1379-1385
Advanced Techniques for Power Optimization and IR Prediction
- Yun-Na Tsai, Shao-Yun Fang:
Via Fabrication with Multi-Row Guiding Templates Using Lamellar DSA. 1386-1391 - Yikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma:
SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. 1392-1398 - Chao-Chi Lan, Chuan-Chi Su, Yuan-Hsiang Lu, Yao-Wen Chang:
Robust Technology-Transferable Static IR Drop Prediction Based on Image-to-Image Machine Learning. 1399-1405 - Bingrui Zhang, Wei Xing, Xin Zhao, Yuquan Sun:
T-Fusion: Thermal Modeling of 3D ICs with Multi-fidelity Fusion. 1406-1412 - Vincent Meyers, Michael Hefenbrock, Mahboobe Sadeghipourrudsari, Dennis Gnad, Mehdi B. Tahoori:
Towards Functional Safety of Neural Network Hardware Accelerators: Concurrent Out-of-Distribution Detection in Hardware Using Power Side-Channel Analysis. 1413-1419
Innovations and Challenges on Cryo-CMOS Devices, Circuits and Design Platforms
- Dondee Navarro, Shin Taniguchi, Chika Tanaka, Kazutoshi Kobayashi, Takashi Sato, Michihiro Shintani:
Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. 1420-1425 - Tetsuro Iwasaki, Takashi Sato, Michihiro Shintani:
Cryo-Compact Modeling Based on Sparse Gaussian Process. 1426-1431 - Yuichiro Mitani, Tatsuya Suzuki, Yohei Miyaki:
Re-Consideration of Correlation Between Interface States and Bulk Traps Using Cryogenic Measurement. 1432-1437 - Takuma Kawakami, Takashi Sato, Hiromitsu Awano:
Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K. 1438-1443 - Takuji Miki:
Cryo-CMOS Analog Circuits for Spin Qubit Control. 1444-1449
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