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ORCIDKenichi Okada 0001
Person information
- affiliation: Tokyo Institute of Technology, Department of Electrical and Electronic Engineering, Tokyo, Japan
- affiliation (PhD 2003): Kyoto University, Department of Communications and Computer Engineering, Kyoto, Japan
Other persons with the same name
- Ken-ichi Okada (aka: Kenichi Okada) — disambiguation page
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2020 – today
- 2024
[j106]Keito Yuasa, Michihiro Ide, Sena Kato, Kenichi Okada, Atsushi Shirane:
Millimeter-Wave Transceiver Utilizing On-Chip Butler Matrix for Simultaneous 5G Relay Communication and Wireless Power Transfer. IEICE Trans. Electron. 107(10): 408-415 (2024)- [j105]Xi Fu
, Dongwon You, Yun Wang, Xiaolin Wang, Ashbir Aviat Fadila, Chenxin Liu, Sena Kato, Chun Wang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada:
A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation. IEEE J. Solid State Circuits 59(2): 349-363 (2024) - [j104]Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Jill C. Mayeda, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang, Jian Pang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada:
A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression. IEEE J. Solid State Circuits 59(4): 978-992 (2024) - [j103]Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada:
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. IEEE J. Solid State Circuits 59(4): 993-1005 (2024) - [j102]Kenichi Okada:
Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium. IEEE J. Solid State Circuits 59(5): 1300 (2024) - [c133]Teruo Jyo, Ibrahim Abdo, Hiroshi Hamada, Munehiko Nagatani, Adam Pander, Hitoshi Wakita, Miwa Mutoh, Yuta Shiratori, Daisuke Kitayama, Carrel da Gomez, Chun Wang, Kota Hatano, Chenxin Liu, Ashbir Aviat Fadila, Jian Pang, Atsushi Shirane, Kenichi Okada, Hiroyuki Takahashi:
300-GHz-Band InP HBT Power Amplifier and InP-CMOS Hybrid Phased-Array Transmitter. BCICTS 2024: 166-172 - [c132]Kenichi Okada:
Sub-THz CMOS Phased-Array Transceiver Design for 6G. ISCAS 2024: 1-4 - [c131]Sidharth Thomas, Jaskirat Singh Virdi, Anshul Verma, Bishnu Prasad Das, Kenichi Okada, Pratap Narayan Singh:
A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases. ISCAS 2024: 1-5 - [c130]Dongfan Xu, Minzhe Tang, Yi Zhang, Zheng Li, Atsushi Shirane, Kenichi Okada:
A 24-71-GHz Tri-Mode Mixer Using Harmonic Selection for Multi-Band 5G NR. ISCAS 2024: 1-4 - [c129]Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada:
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. ISSCC 2024: 192-194 - [c128]Chun Wang, Hans Herdian, Wenbin Zheng, Chenxin Liu, Jill C. Mayeda, Yuxuan Liu, Olivia Angel Yong, Wenqian Wang, Yuncheng Zhang, Carrel da Gomez, Abanob Shehata, Sena Kato, Ibrahim Abdo, Teruo Jyo, Hiroshi Hamada, Hiroyuki Takahashi, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada:
24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS. ISSCC 2024: 415-417 - [c127]Sena Kato, Shu Date, Tao Ruoxin, Yasuto Narukiyo, Hiroki Hayashi, Keito Yuasa, Michihiro Ide, Takashi Tomura, Kenichi Okada, Atsushi Shirane:
A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order Sub-Harmonic Mixer. VLSI Technology and Circuits 2024: 1-2 - [c126]Chenxin Liu, Zheng Li, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Shinsuke Hara, Akifumi Kasamatsu, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada:
A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset. VLSI Technology and Circuits 2024: 1-2 - [c125]Yi Zhang, Minzhe Tang, Jian Pang, Zheng Li, Dongfan Xu, Dingxin Xu, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada:
A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j101]Dongwon You, Xiaolin Wang, Hans Herdian, Xi Fu, Hojun Lee, Michihiro Ide, Carrel da Gomez, Zheng Li, Jill C. Mayeda, Daisuke Awaji, Jian Pang, Hiraku Sakamoto, Kenichi Okada, Atsushi Shirane:
A Ka-Band Deployable Active Phased Array Transmitter Fabricated on 4-Layer Liquid Crystal Polymer Substrate for Small-Satellite Mount. IEEE Access 11: 69522-69535 (2023) - [j100]Zheng Li, Zixin Chen, Qiaoyu Wang, Junqing Liu, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 41-GHz 19.4-dBm Psat CMOS Doherty power amplifier for 5G NR applications. IEICE Electron. Express 20(5): 20220558 (2023) - [j99]Yudai Yamazaki, Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 28GHz High-Accuracy Phase and Amplitude Detection Circuit for Dual-Polarized Phased-Array Calibration. IEICE Trans. Electron. 106(4): 149-156 (2023) - [j98]Zheng Li, Jian Pang, Yi Zhang, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Yun Wang, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Jeehoon Park, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada:
A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station. IEEE J. Solid State Circuits 58(4): 901-914 (2023) - [j97]Yudai Yamazaki, Jun Sakamaki, Jian Pang, Joshua Alvin, Zheng Li, Dongwon You, Jill C. Mayeda, Atsushi Shirane, Kenichi Okada:
A 37-43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD. IEEE J. Solid State Circuits 58(10): 2851-2860 (2023) - [j96]Xi Fu, Dongwon You, Xiaolin Wang, Yun Wang, Carolyn Jill Mayeda, Yuan Gao, Michihiro Ide, Yuncheng Zhang, Jun Sakamaki, Ashbir Aviat Fadila, Zheng Li, Jumpei Sudo, Makoto Higaki, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai, Kenichi Okada, Atsushi Shirane:
A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations. IEEE J. Solid State Circuits 58(12): 3380-3395 (2023) - [c124]Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada:
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. CICC 2023: 1-2 - [c123]Chenxin Liu, Ibrahim Abdo, Chun Wang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada:
A Dual-Mode Bi-Directional CMOS Mixer Using Push-Push Doubler for 300GHz-Band Transceivers. ESSCIRC 2023: 69-72 - [c122]Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Atsushi Shirane, Kenichi Okada:
A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path. ESSCIRC 2023: 265-268 - [c121]Zheng Li, Peng Luo, Jian Pang, Qiaoyu Wang, Atsushi Shirane, Kenichi Okada:
A 24-49-GHz CMOS Area-Efficient Phase-Invariant Mixed-Type Attenuator With Capacitive Compensation for 5G New Radio. ESSCIRC 2023: 449-452 - [c120]Junqing Liu, Zheng Li, Minghao Fan, Yilun Chen, Atsushi Shirane, Kenichi Okada:
A 60-GHz Transformer-Based Power Amplifier Supporting 5G n263-band Applications. ICICDT 2023: 48-51 - [c119]Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, Kenichi Okada:
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. ISSCC 2023: 80-81 - [c118]Xi Fu, Dongwon You, Xiaolin Wang, Michihiro Ide, Yuncheng Zhang, Jun Sakamaki, Ashbir Aviat Fadila, Zheng Li, Yun Wang, Jumpei Sudo, Makoto Higaki, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai, Kenichi Okada, Atsushi Shirane:
A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation. ISSCC 2023: 296-297 - [c117]Dongwon You, Xi Fu, Xiaolin Wang, Yuan Gao, Wenqian Wang, Jun Sakamaki, Hans Herdian, Sena Kato, Michihiro Ide, Yuncheng Zhang, Ashbir Aviat Fadila, Zheng Li, Chun Wang, Yun Wang, Jumpei Sudo, Makoto Higaki, Nahoka Kawaguchi, Masaya Nitta, Soichiro Inoue, Takashi Eishima, Takashi Tomura, Jian Pang, Hiroyuki Sakai, Kenichi Okada, Atsushi Shirane:
A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler. ISSCC 2023: 298-299 - [c116]Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang, Jian Pang, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada:
A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression. VLSI Technology and Circuits 2023: 1-2 - [c115]Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada:
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j95]Junjun Qiu, Bangan Liu, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada:
A low-power digital baseband circuit for GMSK demodulation in sub-GHz application. IEICE Electron. Express 19(12): 20220201 (2022) - [j94]Hiro Tamura, Kiyoshi Yanagisawa, Atsushi Shirane, Kenichi Okada:
Performance Evaluation of Classification and Verification with Quadrant IQ Transition Image. IEICE Trans. Commun. 105-B(5): 580-587 (2022) - [j93]Jian Pang, Xueting Luo, Zheng Li, Atsushi Shirane, Kenichi Okada:
A Compact and High-Resolution CMOS Switch-Type Phase Shifter Achieving 0.4-dB RMS Gain Error for 5G n260 Band. IEICE Trans. Electron. 105-C(3): 102-109 (2022) - [j92]Ibrahim Abdo, Korkut Kaan Tokgoz, Atsushi Shirane, Kenichi Okada:
F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power. IEICE Trans. Electron. 105-C(3): 118-125 (2022) - [j91]Yuncheng Zhang, Bangan Liu, Teruki Someya, Rui Wu, Junjun Qiu, Atsushi Shirane, Kenichi Okada:
A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components. IEICE Trans. Electron. 105-C(7): 334-342 (2022) - [j90]Xi Fu, Yun Wang, Xiaolin Wang, Xiaofan Gu, Xueting Luo, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada:
An 8.5-dB Insertion Loss and 0.8° RMS Phase Error Ka-Band CMOS Hybrid Phase Shifter Featuring Nonuniform Matching for Satellite Communication. IEICE Trans. Electron. 105-C(10): 552-560 (2022) - [j89]Yun Wang, Dongwon You, Xi Fu, Takeshi Nakamura, Ashbir Aviat Fadila, Teruki Someya, Atsuhiro Kawaguchi, Junjun Qiu, Jian Pang, Kiyoshi Yanagisawa, Bangan Liu, Yuncheng Zhang, Haosheng Zhang, Rui Wu, Shunichiro Masaki, Daisuke Yamazaki, Atsushi Shirane, Kenichi Okada:
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. IEEE J. Solid State Circuits 57(2): 356-370 (2022) - [j88]Michihiro Ide, Atsushi Shirane, Kiyoshi Yanagisawa, Dongwon You, Jian Pang, Kenichi Okada:
A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer. IEEE J. Solid State Circuits 57(4): 1211-1223 (2022) - [j87]Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada:
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation. IEEE J. Solid State Circuits 57(8): 2292-2308 (2022) - [j86]Yi Zhang, Jian Pang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada:
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR. IEEE J. Solid State Circuits 57(12): 3617-3630 (2022) - [c114]Kenichi Okada:
Maximizing Energy Efficiency in Sub-THz Radio Communication and Prospective toward 6G. BCICTS 2022: 1-4 - [c113]Teruo Jyo, Hiroshi Hamada, Munehiko Nagatani, Hitoshi Wakita, Ibrahim Abdo, Miwa Mutoh, Yuta Shiratori, Kenichi Okada, Atsushi Shirane, Hiroyuki Takahashi:
A 220-294 GHz Power Amplifier with 10-dBm Psat and 2.2% PAE in 250-nm InP DHBT. BCICTS 2022: 152-155 - [c112]Minzhe Tang, Yi Zhang, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New Radio. ESSCIRC 2022: 333-336 - [c111]Sena Kato, Keito Yuasa, Michihiro Ide, Atsushi Shirane, Kenichi Okada:
A CMOS Full-Wave Switching Rectifier with Frequency Up-Down Conversion for 5G NR Wirelessly-Powered Relay Transceivers. ESSCIRC 2022: 345-348 - [c110]Yudai Yamazaki, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 1.8-67GHz Divide-by-4 ILFD Using Area-Efficient Transformer-Based Injection-Enhancing Technique. ESSCIRC 2022: 393-396 - [c109]Zheng Li, Zixin Chen, Qiaoyu Wang, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 41-GHz 19.4-dBm PSATCMOS Doherty Power Amplifier for 5G NR Applications. ICTA 2022: 32-33 - [c108]Xi Fu, Yun Wang, Dongwon You, Xiaolin Wang, Ashbir Aviat Fadila, Yi Zhang, Sena Kato, Chun Wang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation. ISSCC 2022: 90-92 - [c107]Jian Pang, Yi Zhang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada:
A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR. ISSCC 2022: 434-436 - [c106]Kenichi Okada, Jian Pang, Atsushi Shirane, Zheng Li, Yi Zhang, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro:
Millimeter-Wave CMOS Phased-Array Transceivers for 5G and Beyond. PIMRC 2022: 1-6 - [c105]Michihiro Ide, Yuasa Keito, Sena Kato, Dongwon You, Ashbir Aviat Fadila, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power Transfer. VLSI Technology and Circuits 2022: 96-97 - [c104]Zheng Li, Jian Pang, Yi Zhang, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Zhengyan Guo, Yun Wang, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada:
A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station. VLSI Technology and Circuits 2022: 98-99 - 2021
- [j85]Ibrahim Abdo, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada:
64QAM wireless link with 300GHz InP-CMOS hybrid transceiver. IEICE Electron. Express 18(17): 20210314 (2021) - [j84]Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, Ashbir Aviat Fadila, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Rui Wu, Yun Wang, Dongwon You, Bangan Liu, Zheng Sun, Yuncheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. IEEE J. Solid State Circuits 56(4): 1310-1326 (2021) - [j83]Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Jian Pang, Hanli Liu, Masaya Miyahara, Atsushi Shirane, Kenichi Okada:
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. IEEE J. Solid State Circuits 56(12): 3741-3755 (2021) - [j82]Zheng Sun, Hanli Liu, Hongye Huang, Dexian Tang, Dingxin Xu, Tohru Kaneko, Zheng Li, Jian Pang, Rui Wu, Wei Deng, Atsushi Shirane, Kenichi Okada:
A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 196-209 (2021) - [j81]Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, Aravind Tharayil Narayanan, Haosheng Zhang, Teruki Someya, Atsushi Shirane, Kenichi Okada:
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 603-616 (2021) - [c103]Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Atsushi Shirane, Kenichi Okada:
A DSM-based Polar Transmitter with 23.8% System Efficiency. ASP-DAC 2021: 1-2 - [c102]Ibrahim Abdo, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Atsushi Shirane, Kenichi Okada:
A 0.41W 34Gb/s 300GHz CMOS Wireless Transceiver. ASP-DAC 2021: 3-4 - [c101]Yi Zhang, Jian Pang, Kiyoshi Yanagizawa, Atsushi Shirane, Kenichi Okada:
28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver. ASP-DAC 2021: 7-8 - [c100]Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada:
A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System. ASP-DAC 2021: 93-94 - [c99]Zheng Sun, Dingxin Xu, Junjun Qiu, Zezheng Liu, Yuncheng Zhang, Hongye Huang, Hanli Liu, Bangan Liu, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. ESSCIRC 2021: 499-502 - [c98]Hans Herdian, Takeshi Inoue, Takuichi Hirano, Masatsugu Sogabe, Atsushi Shirane, Kenichi Okada:
Dual-Layer Proton Irradiation for Creating Thermally-Stable High-Resistivity Region in Si CMOS Substrate. ESSDERC 2021: 191-194 - [c97]Yudai Yamazaki, Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 39GHz Divide-by-8 LC-Ring ILFD Designed for 5G New Radio n260 Band. ICTA 2021: 74-75 - [c96]Yi Zhang, Jian Pang, Zheng Li, Atsushi Shirane, Kenichi Okada:
A 28GHz Bi-direction Transceiver with Temperature Compensation. ICTA 2021: 80-81 - [c95]Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada:
22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS. ISSCC 2021: 316-318 - [c94]Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Atsushi Shirane, Kenichi Okada:
32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. ISSCC 2021: 454-456 - [c93]Michihiro Ide, Atsushi Shirane, Kiyoshi Yanagisawa, Dongwon You, Jian Pang, Kenichi Okada:
A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter with 24-GHz Wireless Power and LO Transfer. VLSI Circuits 2021: 1-2 - [c92]Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Weichu Chen, Yun Wang, Dongwon You, Zheng Sun, Yuncheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation. VLSI Circuits 2021: 1-2 - 2020
- [j80]Jian Pang, Ryo Kubozoe, Zheng Li, Masaru Kawabuchi, Atsushi Shirane, Kenichi Okada:
A 28-GHz CMOS Vector-Summing Phase Shifter Featuring I/Q Imbalance Calibration Supporting 11.2Gb/s in 256QAM for 5G New Radio. IEICE Trans. Electron. 103-C(2): 39-47 (2020) - [j79]Zheng Sun, Dingxin Xu, Hongye Huang, Zheng Li, Hanli Liu, Bangan Liu, Jian Pang, Teruki Someya, Atsushi Shirane, Kenichi Okada:
A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications. IEICE Trans. Electron. 103-C(10): 505-513 (2020) - [j78]Yun Wang, Rui Wu, Jian Pang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Xi Fu, Daiki Matsumoto, Takeshi Nakamura, Ryo Kubozoe, Masaru Kawabuchi, Bangan Liu, Haosheng Zhang, Junjun Qiu, Hanli Liu, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS. IEEE J. Solid State Circuits 55(5): 1249-1269 (2020) - [j77]Hiroshi Hamada, Takuya Tsutsumi, Hideaki Matsuzaki, Takuya Fujimura, Ibrahim Abdo, Atsushi Shirane, Kenichi Okada, Go Itami, Ho-Jin Song, Hiroki Sugiyama, Hideyuki Nosaka:
300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers. IEEE J. Solid State Circuits 55(9): 2316-2335 (2020) - [j76]Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Bangan Liu, Aravind Tharayil Narayanan, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Keiichi Motoi, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. IEEE J. Solid State Circuits 55(9): 2371-2386 (2020) - [c91]Zheng Li, Jian Pang, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Joshua Alvin, Bangan Liu, Zheng Sun, Hongye Huang, Atsushi Shirane, Kenichi Okada:
A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. ASP-DAC 2020: 5-6 - [c90]Kenichi Okada, Jian Pang:
Millimeter-Wave CMOS Phased-Array Transceiver Supporting Dual-Polarized MIMO for 5G NR. CICC 2020: 1-8 - [c89]Jian Pang, Xueting Luo, Zheng Li, Atsushi Shirane, Kenichi Okada:
A Compact 37-40GHz CMOS Switch-Type Phase Shifter with Fine-Tuning Stage Achieving 0.4-dB RMS Gain Error. ICTA 2020: 5-6 - [c88]Hiro Tamura, Kiyoshi Yanagisawa, Atsushi Shirane, Kenichi Okada:
Wireless Devices Identification with Light-Weight Convolutional Neural Network Operating on Quadrant IQ Transition Image. NEWCAS 2020: 106-109 - [c87]Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, Ashbir Aviat Fadila, Kiyoshi Yanagisawa, Yi Zhang, Zixin Chen, Zhongliang Huang, Xiaofan Gu, Rui Wu, Yun Wang, Dongwon You, Bangan Liu, Zheng Sun, Yucheng Zhang, Hongye Huang, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation. VLSI Circuits 2020: 1-2 - [c86]Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Kiyoshi Yanagisawa, Junjun Qiu, Yun Wang, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j75]Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Rui Wu, Atsushi Shirane, Kenichi Okada:
A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock. IEICE Trans. Electron. 102-C(4): 276-286 (2019) - [j74]Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. 102-C(7): 520-529 (2019) - [j73]Aravind Tharayil Narayanan, Kenichi Okada:
A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM. IEICE Trans. Electron. 102-C(7): 595-606 (2019) - [j72]Jian Pang, Rui Wu, Yun Wang, Masato Dome, Hisashi Kato, Hongye Huang, Aravind Tharayil Narayanan, Hanli Liu, Bangan Liu, Takeshi Nakamura, Takuya Fujimura, Masaru Kawabuchi, Ryo Kubozoe, Tsuyoshi Miura, Daiki Matsumoto, Zheng Li, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio. IEEE J. Solid State Circuits 54(5): 1228-1242 (2019) - [j71]Yun Wang, Bangan Liu, Rui Wu, Hanli Liu, Aravind Tharayil Narayanan, Jian Pang, Ning Li, Toru Yoshioka, Yuki Terashima, Haosheng Zhang, Dexian Tang, Makihiko Katsuragi, Daeyoung Lee, Sung Tae Choi, Kenichi Okada, Akira Matsuzawa:
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. IEEE J. Solid State Circuits 54(5): 1363-1374 (2019) - [j70]Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada:
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. IEEE J. Solid State Circuits 54(5): 1375-1390 (2019) - [j69]Haosheng Zhang, Hans Herdian, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shigeyoshi Goka, Shinya Yanagimachi, Kenichi Okada:
ULPAC: A Miniaturized Ultralow-Power Atomic Clock. IEEE J. Solid State Circuits 54(11): 3135-3148 (2019) - [j68]Hanli Liu, Atsushi Shirane, Kenichi Okada, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya:
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE J. Solid State Circuits 54(12): 3478-3492 (2019) - [c85]Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto:
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC 2019: 267-270 - [c84]Hiroshi Hamada, Takuya Tsutsumi, Go Itami, Hiroki Sugiyama, Hideaki Matsuzaki, Kenichi Okada, Hideyuki Nosaka:
300-GHz 120-Gb/s Wireless Transceiver with High-Output-Power and High-Gain Power Amplifier Based on 80-nm InP-HEMT Technology. BCICTS 2019: 1-4 - [c83]Kenichi Okada:
Millimeter-Wave CMOS Phased-Array Transceiver Toward 1Tbps Wireless Communication. BCICTS 2019: 1-6 - [c82]Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada:
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC 2019: 1-4 - [c81]Korkut Kaan Tokgoz, Kenichi Okada:
Millimeter-Wave CMOS Transceiver Toward 1Tbps Wireless Communication. ISCAS 2019: 1-4 - [c80]Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada:
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. ISSCC 2019: 256-258 - [c79]Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Aravind Tharayil Narayanan, Bangan Liu, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Keiichi Motoi, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. ISSCC 2019: 344-346 - [c78]Haosheng Zhang, Hans Herdian, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shinya Yanagimachi, Kenichi Okada:
Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping. ISSCC 2019: 462-464 - [c77]Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Yun Wang, Atsushi Shirane, Kenichi Okada:
0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur. VLSI Circuits 2019: 38- - 2018
- [j67]Korkut Kaan Tokgoz, Seitaro Kawai, Kenichi Okada, Akira Matsuzawa:
Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS. IEICE Electron. Express 15(7): 20180067 (2018) - [j66]Bangan Liu, Yun Wang, Jian Pang, Haosheng Zhang, Dongsheng Yang, Aravind Tharayil Narayanan, Dae Young Lee, Sung Tae Choi, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. IEICE Trans. Electron. 101-C(2): 126-134 (2018) - [j65]Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa:
A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. IEICE Trans. Electron. 101-C(4): 187-196 (2018) - [j64]Kenichi Okada:
Foreword. IEICE Trans. Electron. 101-C(7): 430-431 (2018) - [j63]Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada:
A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications. IEEE J. Solid State Circuits 53(12): 3540-3552 (2018) - [j62]Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, Kenichi Okada:
A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. IEEE J. Solid State Circuits 53(12): 3672-3687 (2018) - [c76]Jian Pang, Korkut Kaan Tokgoz, Shotaro Maki, Zheng Li, Xueting Luo, Ibrahim Abdo, Seitarou Kawai, Hanli Liu, Bangan Liu, Makihiko Katsuragi, Kento Kimura, Atsushi Shirane, Kenichi Okada:
A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay. A-SSCC 2018: 77-78 - [c75]Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa:
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC 2018: 1-4 - [c74]Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Rui Wu, Wei Deng, Kenichi Okada:
A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver. ESSCIRC 2018: 310-313 - [c73]Korkut Kaan Tokgoz, Shotaro Maki, Jian Pang, Noriaki Nagashima, Ibrahim Abdo, Seitaro Kawai, Takuya Fujimura, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa:
A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver. ISSCC 2018: 168-170 - [c72]Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa:
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. ISSCC 2018: 246-248 - [c71]Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, Akira Matsuzawa:
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. ISSCC 2018: 444-446 - [c70]Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa:
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. VLSI Circuits 2018: 115-116 - 2017
- [j61]Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. IEICE Trans. Electron. 100-C(3): 259-267 (2017) - [j60]Takuichi Hirano, Ning Li, Kenichi Okada:
Analysis of Effective Material Properties of Metal Dummy Fills in a CMOS Chip. IEICE Trans. Commun. 100-B(5): 793-798 (2017) - [j59]Yun Wang, Makihiko Katsuragi, Kenichi Okada, Akira Matsuzawa:
A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS. IEICE Trans. Electron. 100-C(6): 568-575 (2017) - [j58]Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits 52(11): 2871-2891 (2017) - [c69]Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON 2017: 1025-1028 - [c68]Korkut Kaan Tokgoz, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa:
W-band ultra-high data-rate 65nm CMOS wireless transceiver. ASP-DAC 2017: 5-6 - [c67]Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC 2017: 13-14 - [c66]Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa:
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. ISSCC 2017: 150-151 - [c65]Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC 2017: 424-425 - 2016
- [j57]Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. IEICE Trans. Electron. 99-C(6): 632-640 (2016) - [j56]Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2435-2443 (2016) - [j55]Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits 51(5): 1246-1260 (2016) - [j54]Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits 51(6): 1385-1397 (2016) - [j53]Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. IEEE J. Solid State Circuits 51(7): 1630-1640 (2016) - [j52]Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. IEEE J. Solid State Circuits 51(10): 2345-2356 (2016) - [c64]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC 2016: 1-2 - [c63]Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa:
A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. ASP-DAC 2016: 5-6 - [c62]Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. A-SSCC 2016: 109-112 - [c61]Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC 2016: 197-200 - [c60]Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC 2016: 205-208 - [c59]Korkut Kaan Tokgoz, Shotaro Maki, Seitaro Kawai, Noriaki Nagashima, Jun Emmei, Masato Dome, Hisashi Kato, Jian Pang, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Yuuki Seo, Kimsrun Lim, Shinji Sato, Ning Li, Kengo Nakata, Kenichi Okada, Akira Matsuzawa:
13.3 A 56Gb/s W-band CMOS wireless transceiver. ISSCC 2016: 242-243 - [c58]Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC 2016: 248-249 - [c57]Kenichi Okada, Jan van Sinderen:
Session 26 overview: Wireless for IoE. ISSCC 2016: 434-435 - [c56]Stefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic:
F3: Radio architectures and circuits towards 5G. ISSCC 2016: 498-501 - 2015
- [j51]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa:
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express 12(15): 20150531 (2015) - [j50]Korkut Kaan Tokgoz, Kimsrun Lim, Seitarou Kawai, Nurul Fajri, Kenichi Okada, Akira Matsuzawa:
Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Electron. 98-C(1): 35-44 (2015) - [j49]Rui Wu, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa:
A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. IEICE Trans. Electron. 98-C(4): 304-314 (2015) - [j48]Kenichi Okada:
Digitally Assisted Analog and RF Circuits. IEICE Trans. Electron. 98-C(6): 461-470 (2015) - [j47]Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. IEICE Trans. Electron. 98-C(6): 471-479 (2015) - [j46]Kento Kimura, Aravind Tharayil Narayanan, Kenichi Okada, Akira Matsuzawa:
An AM-PM Noise Mitigation Technique in Class-C VCO. IEICE Trans. Electron. 98-C(12): 1161-1170 (2015) - [j45]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits 50(1): 68-80 (2015) - [j44]Angelo Nagari, Kenichi Okada, Marian Verhelst:
Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 50(7): 1512-1515 (2015) - [j43]Makoto Takamiya, Jieh-Tsorng Wu, Jussi Ryynänen, Kenichi Okada, Jaeha Kim:
Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 50(12): 2799-2803 (2015) - [c55]Kenichi Okada:
A 28-Gb/s 60-GHz wireless transceiver in 65nm CMOS with 64QAM capability. ASICON 2015: 1-4 - [c54]Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC 2015: 2-3 - [c53]Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A tail-current modulated VCO with adaptive-bias scheme. ASP-DAC 2015: 36-37 - [c52]Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC 2015: 42-43 - [c51]Teerachot Siriburanon, Hanli Liu, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa:
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. ESSCIRC 2015: 76-79 - [c50]Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. ESSCIRC 2015: 380-383 - [c49]Ning Li, Takeshi Inoue, Takuichi Hirano, Jian Pang, Rui Wu, Kenichi Okada, Hitoshi Sakane, Akira Matsuzawa:
Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process. ESSDERC 2015: 254-257 - [c48]Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. ISSCC 2015: 1-3 - [c47]Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC 2015: 1-3 - [c46]Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
19.5 An HCI-healing 60GHz CMOS transceiver. ISSCC 2015: 1-3 - 2014
- [j42]Rui Wu, Yuuki Tsukui, Ryo Minami, Kenichi Okada, Akira Matsuzawa:
A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation. IEICE Trans. Electron. 97-C(8): 803-812 (2014) - [j41]Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits 49(1): 50-60 (2014) - [j40]Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. IEEE J. Solid State Circuits 49(9): 1984-1994 (2014) - [c45]Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC 2014: 21-22 - [c44]Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. ASP-DAC 2014: 25-26 - [c43]Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs. A-SSCC 2014: 181-184 - [c42]Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. A-SSCC 2014: 285-288 - [c41]Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. ESSCIRC 2014: 343-346 - [c40]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. ISSCC 2014: 266-267 - [c39]Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa:
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. ISSCC 2014: 346-347 - [c38]Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa:
22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. ISSCC 2014: 388-389 - 2013
- [j39]Hamid Kiumarsi, Hiroyuki Ito, Kenichi Okada, Yusuke Uemichi, Yasuto Chiba, Noboru Ishihara, Kazuya Masu:
A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate. IEICE Electron. Express 10(2): 20120901 (2013) - [j38]Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs. IEICE Trans. Electron. 96-C(4): 577-585 (2013) - [j37]Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. IEICE Trans. Electron. 96-C(6): 804-812 (2013) - [j36]Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa:
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. IEEE J. Solid State Circuits 48(1): 46-65 (2013) - [j35]Wei Deng, Kenichi Okada, Akira Matsuzawa:
Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. IEEE J. Solid State Circuits 48(2): 429-440 (2013) - [j34]Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. IEEE J. Solid State Circuits 48(7): 1710-1720 (2013) - [c37]Seitaro Kawai, Ryo Minami, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Yuki Tsukui, Kenichi Okada, Akira Matsuzawa:
A full 4-channel 60 GHz direct-conversion transceiver. ASP-DAC 2013: 95-96 - [c36]Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. ASP-DAC 2013: 97-98 - [c35]Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. ASP-DAC 2013: 99-100 - [c34]Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. ESSCIRC 2013: 403-406 - [c33]Brian A. Floyd, Kenichi Okada:
Session 13 overview: High-performance wireless. ISSCC 2013: 228-229 - [c32]Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. ISSCC 2013: 248-249 - [c31]Yuki Tsukui, Kenichi Okada, Akira Matsuzawa:
A 60 GHz up-conversion mixer using asymmetric layout with -41.1 dBc LO leakage. LASCAS 2013: 1-4 - 2012
- [j33]Jee Young Hong, Daisuke Imanishi, Kenichi Okada, Akira Matsuzawa:
Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning. IEICE Trans. Electron. 95-C(2): 290-296 (2012) - [j32]Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa:
A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 498-505 (2012) - [j31]Kenichi Okada, You Nomiyama, Rui Murakami, Akira Matsuzawa:
A Dual-Conduction Class-C VCO for a Low Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 506-514 (2012) - [j30]Qinghong Bu, Ning Li, Kenichi Okada, Akira Matsuzawa:
Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Electron. 95-C(5): 942-948 (2012) - [j29]Wei Deng, Kenichi Okada, Akira Matsuzawa:
A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition. IEICE Trans. Electron. 95-C(7): 1285-1296 (2012) - [j28]Toshihiko Ito, Kenichi Okada, Akira Matsuzawa:
A Wideband Common-Gate Low-Noise Amplifier Using Capacitive Feedback. IEICE Trans. Electron. 95-C(10): 1666-1674 (2012) - [j27]Toshihiko Ito, Masaki Kanemaru, Satoshi Furuya, Dong Ta Ngoc Huy, Kenichi Okada, Akira Matsuzawa:
Inter-Stage Tunable Notch Filter for a Multi-Band WCDMA Receiver. IEICE Trans. Electron. 95-C(11): 1776-1782 (2012) - [j26]Woogeun Rhee, Antonio Liscidini, Jae-Yoon Sim, Kenichi Okada, Sudhakar Pamarti:
Clock/Frequency Generation Circuits and Systems. J. Electr. Comput. Eng. 2012: 941653:1-941653:2 (2012) - [c30]Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada, Akira Matsuzawa:
A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS. ASP-DAC 2012: 467-468 - [c29]Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios. ASP-DAC 2012: 559-560 - [c28]Wei Deng, Kenichi Okada, Akira Matsuzawa:
A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. ASP-DAC 2012: 563-564 - [c27]Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. ESSCIRC 2012: 201-204 - [c26]Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa:
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. ISSCC 2012: 218-220 - 2011
- [j25]Rui Murakami, Toshihiko Ito, Kenichi Okada, Akira Matsuzawa:
An ultra-compact LC-VCO using a stacked-spiral inductor. IEICE Electron. Express 8(7): 512-517 (2011) - [j24]Ning Li, Kota Matsushita, Kenichi Okada, Akira Matsuzawa:
A 14.3% PAE parallel class-A and AB 60GHz CMOS PA. IEICE Electron. Express 8(13): 1071-1074 (2011) - [j23]Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Rui Ito, Takahiro Sekiguchi, Mototsugu Hamada, Kenichi Okada:
A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 592-602 (2011) - [j22]Yuya Ono, Takuichi Hirano, Kenichi Okada, Jiro Hirokawa, Makoto Ando:
Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate. IEICE Trans. Electron. 94-C(6): 1008-1015 (2011) - [j21]Ryo Minami, Jee Young Hong, Kenichi Okada, Akira Matsuzawa:
Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip. IEICE Trans. Electron. 94-C(6): 1057-1060 (2011) - [j20]Jee Young Hong, Daisuke Imanishi, Kenichi Okada, Akira Matsuzawa:
Tunable CMOS Power Amplifiers for Reconfigurable Transceivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(11): 2394-2401 (2011) - [j19]Ning Li, Qinghong Bu, Kota Matsushita, Naoki Takayama, Shogo Ito, Kenichi Okada, Akira Matsuzawa:
Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving. IEICE Trans. Electron. 94-C(12): 1881-1888 (2011) - [j18]Yusaku Ito, Kenichi Okada, Kazuya Masu:
A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers. J. Electr. Comput. Eng. 2011: 361910:1-361910:7 (2011) - [j17]Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa:
A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications. IEEE J. Solid State Circuits 46(11): 2635-2649 (2011) - [j16]Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa:
A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c. IEEE J. Solid State Circuits 46(12): 2988-3004 (2011) - [c25]Takahiro Sato, Kenichi Okada, Akira Matsuzawa:
A new figure of Merit of LC oscilators considering frequency tuning range. ASICON 2011: 586-589 - [c24]Kenichi Okada:
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver. ASICON 2011: 1022-1025 - [c23]Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa:
A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. ASP-DAC 2011: 101-102 - [c22]Wei Deng, Kenichi Okada, Akira Matsuzawa:
An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. ASP-DAC 2011: 103-104 - [c21]Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing. A-SSCC 2011: 85-88 - [c20]Hiroki Asada, Keigo Bunsen, Kota Matsushita, Rui Murakami, Qinghong Bu, Ahmed Musa, Takahiro Sato, Tatsuya Yamaguchi, Ryo Minami, Toshihiko Ito, Kenichi Okada, Akira Matsuzawa:
A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS. A-SSCC 2011: 373-376 - [c19]Wei Deng, Kenichi Okada, Akira Matsuzawa:
A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. ESSCIRC 2011: 499-502 - [c18]Kenichi Okada:
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver. ISOCC 2011: 20-23 - [c17]Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa:
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. ISSCC 2011: 160-162 - 2010
- [j15]Shoichi Hara, Rui Murakami, Kenichi Okada, Akira Matsuzawa:
The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 424-430 (2010) - [j14]Ning Li, Kota Matsushita, Naoki Takayama, Shogo Ito, Kenichi Okada, Akira Matsuzawa:
Evaluation of a Multi-Line De-Embedding Technique up to 110 GHz for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 431-439 (2010) - [j13]Shoichi Hara, Kenichi Okada, Akira Matsuzawa:
A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider. IEICE Trans. Electron. 93-C(6): 763-769 (2010) - [j12]Rui Murakami, Shoichi Hara, Kenichi Okada, Akira Matsuzawa:
Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators. IEICE Trans. Electron. 93-C(6): 777-784 (2010) - [j11]Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Keigo Bunsen, Kenichi Okada, Akira Matsuzawa:
A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling. IEICE Trans. Electron. 93-C(6): 812-819 (2010) - [c16]Daisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa:
A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters. ASP-DAC 2010: 351-352 - [c15]Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa:
A 60GHz direct-conversion transmitter in 65nm CMOS technology. ASP-DAC 2010: 363-364 - [c14]Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa:
A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. ESSCIRC 2010: 342-345
2000 – 2009
- 2009
- [j10]Hirotaka Sugawara, Kenichi Okada, Kazuya Masu:
Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 401-410 (2009) - [j9]Takeshi Ito, Kenichi Okada, Kazuya Masu:
Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1590-1597 (2009) - 2008
- [j8]Kazuya Masu, Kenichi Okada:
Reconfigurable RF CMOS Circuit for Cognitive Radio. IEICE Trans. Commun. 91-B(1): 10-13 (2008) - [j7]Ning Li, Win Chaivipas, Kenichi Okada, Akira Matsuzawa:
Analysis of CMOS Transconductance Amplifiers for Sampling Mixers. IEICE Trans. Electron. 91-C(6): 871-878 (2008) - [j6]Win Chaivipas, Kenichi Okada, Akira Matsuzawa:
Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators. IEICE Trans. Electron. 91-C(6): 918-927 (2008) - [c13]Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu:
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. ASP-DAC 2008: 97-98 - [c12]Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa:
A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. ASP-DAC 2008: 103-104 - [c11]Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu:
Small-area CMOS RF distributed mixer using multi-port inductors. ASP-DAC 2008: 105-106 - [c10]Shoichi Hara, Takeshi Ito, Kenichi Okada, Akira Matsuzawa:
Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. ISCAS 2008: 1966-1969 - 2007
- [c9]Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu:
Adaptable wire-length distribution with tunable occupation probability. SLIP 2007: 1-8 - 2006
- [j5]Takumi Uezono, Kenichi Okada, Kazuya Masu:
Statistical Modeling of a Via Distribution for Yield Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3579-3584 (2006) - [c8]Takumi Uezono, Kenichi Okada, Kazuya Masu:
Via Distribution Model for Yield Estimation. ISQED 2006: 479-484 - [c7]Kenichi Okada, Takumi Uezono, Kazuya Masu:
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. PATMOS 2006: 181-190 - 2005
- [j4]Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu:
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3358-3366 (2005) - [j3]Hidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu:
Evaluation of X Architecture Using Interconnect Length Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3437-3444 (2005) - [j2]Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu:
Wire Length Distribution Model for System LSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3445-3452 (2005) - [c6]Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu:
Evaluation of on-chip transmission line interconnect using wire length distribution. ASP-DAC 2005: 133-138 - [c5]Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu:
A dynamic reconfigurable RF circuit architecture. ASP-DAC 2005: 683-686 - [c4]Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu:
Prediction of delay time for future LSI using on-chip transmission line interconnects. SLIP 2005: 7-12 - 2004
- [j1]Yoshiaki Yoshihara, Hirotaka Sugawara, Hiroyuki Ito, Kenichi Okada, Kazuya Masu:
Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design. IEICE Electron. Express 1(7): 156-159 (2004) - 2003
- [c3]Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera:
A statistical gate delay model for intra-chip and inter-chip variabilities. ASP-DAC 2003: 31-36 - [c2]Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera:
Statistical modeling of gate-delay variation with consideration of intra-gate variability. ISCAS (5) 2003: 513-516 - 2000
- [c1]Kenichi Okada, Hidetoshi Onodera:
Statistical modeling of device characteristics with systematic fluctuation. ISCAS 2000: 437-440
Coauthor Index
[j82] [j81] [j68] [c82] [c80] [j65] [j63] [j62] [c75] [c74] [c72] [c71] [j61] [c67] [j57] [j55] [j54] [j53] [c64] [c61] [j51] [j49] [j47] [j45] [c54] [c53] [c52] [c51] [c50] [c48] [c47] [j41] [j40] [c45] [c44] [c43] [c42] [c41] [c40] [j37] [j35] [j34] [c36] [c35] [c34] [c32] [j29] [c28] [c27] [c22] [c19]
Seitaro Kawai
aka: Seitarou Kawai
aka: Seitarou Kawai
[j74] [j71] [j67] [j66] [j65] [c75] [c73] [c72] [c71] [c70] [j61] [j59] [j58] [c69] [c68] [c67] [c66] [c65] [j57] [j56] [j55] [j54] [j53] [j52] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [j51] [j50] [j49] [j47] [j46] [j45] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [j42] [j41] [j40] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [j38] [j37] [j36] [j35] [j34] [c37] [c36] [c35] [c34] [c32] [c31] [j33] [j32] [j31] [j30] [j29] [j28] [j27] [c30] [c29] [c28] [c27] [c26] [j25] [j24] [j21] [j20] [j19] [j17] [j16] [c25] [c23] [c22] [c21] [c20] [c19] [c17] [j15] [j14] [j13] [j12] [j11] [c16] [c15] [c14] [j7] [j6] [c12] [c10]
[j105] [j104] [c133] [c125] [j101] [j100] [j99] [j98] [j97] [j96] [c121] [c118] [c117] [c116] [j93] [j90] [j89] [j88] [j87] [j86] [c112] [c110] [c109] [c108] [c107] [c106] [c105] [c104] [j84] [j83] [j82] [j81] [c101] [c100] [c99] [c97] [c96] [c95] [c93] [c92] [j80] [j79] [j78] [j76] [c91] [c90] [c89] [c87] [c86] [j72] [j71] [j70] [j68] [c82] [c80] [c79] [j66] [c76] [c75] [c73] [j58] [c69] [c65] [c62] [c59] [c49]
[j106] [j105] [j104] [j103] [c133] [c130] [c129] [c128] [c127] [c126] [c125] [j101] [j100] [j99] [j98] [j97] [j96] [c124] [c123] [c122] [c121] [c120] [c119] [c118] [c117] [c116] [c115] [j95] [j94] [j93] [j92] [j91] [j90] [j89] [j88] [j87] [j86] [c113] [c112] [c111] [c110] [c109] [c108] [c107] [c106] [c105] [c104] [j85] [j84] [j83] [j82] [j81] [c103] [c102] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [j80] [j79] [j78] [j77] [j76] [c91] [c89] [c88] [c87] [c86] [j75] [j72] [j70] [j69] [j68] [c82] [c80] [c79] [c78] [c77] [c76]
Kiyoshi Yanagisawa
aka: Kiyoshi Yanagizawa
aka: Kiyoshi Yanagizawa
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