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2020 – today
- 2024
[j16]Wei Liu
, Shanlin Xiao, Yue Liu, Zhiyi Yu:
SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule. IEEE Trans. Biomed. Circuits Syst. 18(5): 1156-1165 (2024)- [j15]Huiyao Wang, Shanlin Xiao, Lingfeng Zhou, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3920-3924 (2024) - [j14]Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1045-1057 (2024) - [j13]Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1852-1863 (2024) - [c16]Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint. DATE 2024: 1-6 - [c15]Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu:
Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. ICASSP 2024: 6410-6414 - 2023
- [c14]Zeyang Xu, Shanlin Xiao, Lingfeng Zhou, Bohan Wang, Zhiyi Yu:
Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement. ICTA 2023: 35-36 - [c13]Kexin Huang, Wei Liu, Yue Liu, Shanlin Xiao, Zhiyi Yu:
Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient. ICTA 2023: 89-90 - [i5]Jilong Luo, Shanlin Xiao, Yinsheng Chen, Zhiyi Yu:
Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks. CoRR abs/2310.12985 (2023) - [i4]Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu:
SparseSpikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. CoRR abs/2311.08806 (2023) - 2022
- [j12]Wenzha Yang, Yong Ma, Jiajie Yan, Yang Chen, Shanlin Xiao, Zhiyi Yu:
A dual-rail/single-rail hybrid system using null convention logic circuits. Microelectron. J. 125: 105446 (2022) - [j11]Yuhao Huang, Shanlin Xiao, Zhiyu Li, Zhiyi Yu:
An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3904-3908 (2022) - [c12]Ruimin Zhu, Zeyang Xu, Yuhao Huang, Shanlin Xiao, Zhiyi Yu:
DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits. ICTA 2022: 88-89 - 2021
- [j10]Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu:
Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks. IEICE Electron. Express 18(24): 20210491 (2021) - [j9]Mingyuan Meng, Xingyu Yang, Lei Bi, Jinman Kim, Shanlin Xiao, Zhiyi Yu:
High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning. Neurocomputing 441: 92-104 (2021) - [j8]Qiang Zhang, Shanlin Xiao, Zhiyi Yu, Huanliang Zheng, Peng Wang:
Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing. J. Electronic Imaging 30(6) (2021) - [j7]Shanlin Xiao, Weikun Liu, Junshu Lin, Zhiyi Yu:
A Data-Driven Asynchronous Neural Network Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1874-1886 (2021) - [j6]Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, Zhiyi Yu:
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3153-3157 (2021) - [j5]Huanliang Zheng, Yuhao Guo, Xingyu Yang, Shanlin Xiao, Zhiyi Yu:
Balancing the Cost and Performance Trade-Offs in SNN Processors. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3172-3176 (2021) - [c11]Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu:
3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA. FCCM 2021: 181-185 - [c10]Jian Wang, Huipeng Deng, Huafeng Ye, Shanlin Xiao, Zhiyi Yu:
FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs. ICTA 2021: 72-73 - [c9]Qingyi Xie, Ziyuan Luo, Shanlin Xiao, Kai Wang, Zhiyi Yu:
High-Throughput Zipper Encoder for 800G Optical Communication System. ICTA 2021: 214-215 - [c8]Ziyuan Luo, Qingyi Xie, Shanlin Xiao, Zhiyi Yu:
A high throughput spatially coupled low density generator matrix coding system. ICTA 2021: 228-229 - 2020
- [j4]Shanlin Xiao, Wei Liu, Yuhao Guo, Zhiyi Yu:
Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing. IEEE Trans. Biomed. Circuits Syst. 14(5): 942-950 (2020) - [j3]Shanlin Xiao, Yuhao Guo, Wenkang Liao, Huipeng Deng, Yi Luo, Huanliang Zheng, Jian Wang, Cheng Li, Gezi Li, Zhiyi Yu:
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 1966-1978 (2020) - [c7]Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu:
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. ICPR 2020: 6417-6424 - [c6]Junshu Lin, Weikun Liu, Xusheng Li, Shanlin Xiao, Zhiyi Yu:
An Asynchronous Convolution Process Engine forVGG-16 Neural Network. ICTA 2020: 73-74 - [c5]Weikun Liu, Junshu Lin, Xusheng Li, Shanlin Xiao, Zhiyi Yu:
A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs. ICTA 2020: 79-80 - [c4]Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu:
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. IJCNN 2020: 1-8 - [c3]Wenkang Liao, Yuhao Guo, Shanlin Xiao, Zhiyi Yu:
A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection. ISCAS 2020: 1-5 - [i3]Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu:
BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network. CoRR abs/2001.01680 (2020) - [i2]Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu:
Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. CoRR abs/2001.10696 (2020) - [i1]Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu:
SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. CoRR abs/2010.09690 (2020)
2010 – 2019
- 2018
- [c2]Xiaobai Chen, Shanlin Xiao, Zhiyi Yu:
A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration. APSIPA 2018: 1402-1405 - 2017
- [j2]Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1384-1395 (2017) - [j1]Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
HOG-Based Object Detection Processor Design Using ASIP Methodology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2972-2984 (2017) - 2016
- [c1]Shanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
An efficient embedded processor for object detection using ASIP methodology. ASAP 2016: 225-226
Coauthor Index
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last updated on 2024-10-23 21:26 CEST by the dblp team
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