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2020 – today
- 2025
[j31]Eunji Song, Jeonghyu Yang, Youngmin Oh, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Taeho Shin, Jaeduk Han:
100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology. IEEE J. Solid State Circuits 60(2): 543-554 (2025)- 2024
- [j30]Sungweon Hong
, Yunseob Tae, Dongjun Lee, Gijin Park, Jaemyung Lim, Kyungjun Cho, Chunseok Jeong, Myeong-Jae Park, Songnam Hong, Jaeduk Han:
Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology. IEEE Access 12: 104473-104489 (2024) - [j29]Hyuntae Kim, Yunseong Jo, Sanghun Lee, Eunsang Lee, Young Choi, Jaewoo Park, Myoungbo Kwak, Jung-Hwan Choi, Youngdon Choi, Jaeduk Han:
A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 4912-4923 (2024) - [j28]Eunji Song, Jiyun Han, Hyeongmin Seo, Hyuntae Kim, Hyunwoo Im, Jaeduk Han:
A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Techniques. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 46-50 (2024) - [j27]Taeyang Sim, Sun-Ho Yeom, Hyunwoo Im, Youngmin Oh, Hyeongmin Seo, Hyeongjun Ko, Hankyu Chi, Hae-Kang Jung, Jaeduk Han:
A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1012-1016 (2024) - [j26]Wookjin Shin, Hyeongmin Seo, Sangwan Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Jaeduk Han:
A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1819-1823 (2024) - [j25]Youngmin Oh, Hyunwoo Im, Jeonghyu Yang, Eunji Song, Dongjun Lee, Sangwan Lee, Taeho Shin, Jaeduk Han:
A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 2936-2940 (2024) - [j24]Sanghun Lee, Jaemyung Lim, Jaeduk Han:
A PSRR-Enhanced Fast-Response Inverter-Based LDO for Mobile Devices. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3226-3230 (2024) - [j23]Gijin Park, Sun-Ho Yeom, InWoo Jang, Dongjun Lee, Jaeduk Han, Min-Seong Choo:
3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4091-4095 (2024) - [j22]Sangwan Lee, Hyeongmin Seo, Seungwoo Son, Sunoh Yeom, Jaeduk Han:
A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4623-4627 (2024) - [c34]Ali Mosleh, Luxi Zhao, Atin Singh, Jaeduk Han, Abhijith Punnappurath, Marcus A. Brubaker, Jihwan Choe, Michael S. Brown:
Non-parametric Sensor Noise Modeling and Synthesis. ECCV (24) 2024: 73-89 - [c33]Zhongkai Wang, Minsoo Choi, Paul Kwon, Zhaokai Liu, Bozhi Yin, Kyoungtae Lee, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. ISCAS 2024: 1-5 - [c32]Yunseong Jo, Hyuntae Kim, Jaeduk Han:
Analysis of Test Environment Configuration for High-Speed Link Chip Measurement. ISOCC 2024: 430-431 - [c31]Jonghyeon Nam, Jaeduk Han, Hokeun Kim:
Low-Power Encoding for PAM-3 DRAM Bus. SMACD 2024: 1-4 - [i3]Geunyoung You, Youjin Byun, Sojin Lim, Jaeduk Han:
Interactive and Automatic Generation of Primitive Custom Circuit Layout Using LLMs. CoRR abs/2408.07279 (2024) - [i2]Jonghyeon Nam, Jaeduk Han, Hokeun Kim:
Low-Power Encoding for PAM-3 DRAM Bus. CoRR abs/2410.12990 (2024) - 2023
- [j21]Dongjun Lee, Gijin Park, Jaeduk Han, Min-Seong Choo:
An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies. IEEE Access 11: 7530-7539 (2023) - [j20]Taeho Shin, Dongjun Lee, Dongwhee Kim, Gaeryun Sung, Wookjin Shin, Yunseong Jo, Hyungjoo Park, Jaeduk Han:
LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4402-4412 (2023) - [j19]Kunmo Kim, Suhong Moon, Jaeduk Han, Elad Alon, Ali M. Niknejad:
Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 4169-4182 (2023) - [j18]Hyeongmin Seo, Jiyun Han, Kyungmin Kim, Baek-Jin Lim, EunSeok Shin, Youngdon Choi, Hyungjong Ko, Jung-Hwan Choi, Sang-Hyun Lee, Changsik Yoo, Jaeduk Han:
A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 411-415 (2023) - [j17]Hyuntae Kim, Hyeongmin Seo, Yunseong Jo, Changsik Yoo, Jaeduk Han:
An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1301-1305 (2023) - [j16]Hyochang Kim, Hyeongmin Seo, Hyuntae Kim, Changsik Yoo, Jaeduk Han:
A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2799-2803 (2023) - [c30]Sun-Ho Yeom, Taeyang Sim, Jaeduk Han:
An Analysis of CMOS Latched Comparators. ICEIC 2023: 1-4 - [c29]Youngmin Oh, Taeyang Sim, Jaeduk Han:
Analysis of Grounded Coplanar Waveguide (GCPW) for High-Speed Links Channel. ISOCC 2023: 117-118 - [c28]Jihoon Jang, Heedo Jeong, Jaeduk Han:
Multi-Phase Frequency Divider Generator with Process-Independent Automation. ISOCC 2023: 129-130 - [c27]Bona Lim, Hanhee Jo, Jaeduk Han:
An Analysis of Current-mode Drivers in 40-nm CMOS Technology. ISOCC 2023: 355-356 - [c26]Jeonghyu Yang, Eunji Song, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Taeho Shin, Jaeduk Han:
A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm. ISSCC 2023: 122-123 - 2022
- [j15]Taeung No, Seonjun Choi, Gaeryun Sung, Seong-Beom Kim, Jaeduk Han, Yun Heub Song:
A Discharge-Path-Based Sensing Circuit With OTS Snapback Current Protection for Phase Change Memories. IEEE Access 10: 53513-53521 (2022) - [j14]Zhongkai Wang, Minsoo Choi, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. IEEE J. Solid State Circuits 57(1): 21-31 (2022) - [j13]Eunsang Lee, Changhyun Pyo, Sanghun Lee, Jaeduk Han:
A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3954-3964 (2022) - [c25]Youri Su, Sanghun Lee, Eunji Song, Dongha Kim, Jaeduk Han, Hokeun Kim:
Energy-Efficient Bus Encoding Techniques for Next-Generation PAM-4 DRAM Interfaces. ICCD 2022: 693-700 - [c24]Zhongkai Wang, Minsoo Choi, John Charles Wright, Kyoungtae Lee, Zhaokai Liu, Bozhi Yin, Jaeduk Han, Sijun Du, Elad Alon:
A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow. ISCAS 2022: 2881-2885 - [c23]Eunji Song, Jeonghyu Yang, Seungwook Hong, Jaeduk Han:
A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications. MWSCAS 2022: 1-4 - [c22]Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. VLSI Technology and Circuits 2022: 34-35 - [i1]Taeho Shin, Dongjun Lee, Dongwhee Kim, Gaeryun Sung, Wookjin Shin, Yunseong Jo, Hyungjoo Park, Jaeduk Han:
A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids. CoRR abs/2207.11728 (2022) - 2021
- [j12]Jaeduk Han, Haegeun Lee, Moon Gi Kang:
Thermal Image Restoration Based on LWIR Sensor Statistics. Sensors 21(16): 5443 (2021) - [j11]Haegeun Lee, Jaeduk Han, Soonyoung Hong, Moon Gi Kang:
Automatic prior selection for image deconvolution: Statistical modeling on natural images. Signal Process. 189: 108307 (2021) - [j10]Jaeduk Han, Woo-Rham Bae, Eric Chang, Zhongkai Wang, Borivoje Nikolic, Elad Alon:
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1012-1022 (2021) - [c21]Youngbog Yoon, Daeyong Han, Shinho Chu, Sangho Lee, Jaeduk Han, Junhyun Chun:
Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies. DATE 2021: 721-722 - [c20]Dongjun Lee, Jaeduk Han:
Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology. ISOCC 2021: 292-293 - [c19]Taeho Shin, Jaeduk Han:
A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits. ISOCC 2021: 335-336 - [c18]Gaeryun Sung, Jaeduk Han:
High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology. ISOCC 2021: 377-378 - [c17]Minsoo Choi, Zhongkai Wang, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Elad Alon:
8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS. ISSCC 2021: 128-130 - 2020
- [j9]Jonghyun Kim, Jaeduk Han, Moon Gi Kang:
Multi-Frame Depth Super-Resolution for ToF Sensor With Total Variation Regularized L1 Function. IEEE Access 8: 165810-165826 (2020) - [j8]Jaeduk Han, Soonyoung Hong, Moon Gi Kang:
Canonical Illumination Decomposition and Its Applications. IEEE Trans. Circuits Syst. Video Technol. 30(11): 4158-4170 (2020) - [c16]Jaeduk Han, Soonyoung Hong, Moon Gi Kang:
Computational Color Constancy under Multiple Light Sources. Image Processing: Algorithms and Systems 2020 - [c15]Taeung No, Jaeduk Han:
Design Techniques for Robust and Area-efficient Current Sources in Nanometer CMOS Technology. ISOCC 2020: 232-233
2010 – 2019
- 2019
- [j7]Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Orhan Ocal, Paul Rigge, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic:
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. IEEE J. Solid State Circuits 54(7): 1993-2008 (2019) - [j6]Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits 54(10): 2786-2801 (2019) - [c14]Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon:
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. CICC 2019: 1-4 - [c13]Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, Elad Alon:
A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit. ESSCIRC 2019: 273-276 - [c12]Haegeun Lee, Jonghyun Kim, Jaeduk Han, Moon Gi Kang:
Multi-frame super-resolution utilizing spatially adaptive regularization for ToF camera. Image Processing: Algorithms and Systems 2019 - [c11]Jaeduk Han, Eric Chang, Elad Alon:
Design and Automatic Generation of High-Speed Circuits for Wireline Communications. ISOCC 2019: 40-41 - 2018
- [j5]Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong:
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. IEEE Trans. Ind. Electron. 65(7): 5979-5989 (2018) - [j4]Jaeduk Han, Ki-Sun Song, Jonghyun Kim, Moon Gi Kang:
Permuted Coordinate-Wise Optimizations Applied to Lp-Regularized Image Deconvolution. IEEE Trans. Image Process. 27(7): 3556-3570 (2018) - [c10]Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC 2018: 285-288 - [c9]Eric Chang, Jaeduk Han, Woo-Rham Bae, Zhongkai Wang, Nathan Narevsky, Borivoje Nikolic, Elad Alon:
BAG2: A process-portable framework for generator-based AMS circuit design. CICC 2018: 1-8 - [c8]Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic:
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. ESSCIRC 2018: 322-325 - [c7]Eric Chang, Nathan Narevsky, Jaeduk Han, Elad Alon:
An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit. VLSI Circuits 2018: 153-154 - 2017
- [j3]Jaeduk Han, Nicholas Sutardja, Yue Lu, Elad Alon:
Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology. IEEE J. Solid State Circuits 52(12): 3474-3485 (2017) - [j2]Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang:
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. IEEE J. Solid State Circuits 52(12): 3486-3502 (2017) - [c6]Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolic:
A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET. A-SSCC 2017: 305-308 - [c5]Jaeduk Han, Jonghyun Kim, Moon Gi Kang:
Non-blind Image Deconvolution using Sampling without Replacement. Image Processing: Algorithms and Systems 2017: 125-130 - [c4]Jaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon:
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology. ISSCC 2017: 112-113 - [c3]Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang:
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. ISSCC 2017: 114-115 - 2016
- [j1]Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon:
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology. IEEE J. Solid State Circuits 51(4): 871-880 (2016) - 2015
- [c2]Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon:
A 60Gb/s 173mW receiver frontend in 65nm CMOS technology. VLSIC 2015: 230- - 2011
- [c1]Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jaeduk Han, Sunkwon Kim, Kyu-Sang Park, Dong-Hyuk Lim, Jung-Hoon Chun, Deog-Kyoon Jeong, Suhwan Kim:
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. ISSCC 2011: 494-496
Coauthor Index
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