"Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm ..."

Jaeduk Han et al. (2016)

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DOI: 10.1109/JSSC.2016.2519389

access: closed

type: Journal Article

metadata version: 2022-10-27

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Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon:
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology. IEEE J. Solid State Circuits 51(4): 871-880 (2016)

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