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ORCIDNicholas Sutardja
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2010 – 2019
- 2019
[c5]Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, Elad Alon:
A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit. ESSCIRC 2019: 273-276- 2017
- [j3]Jaeduk Han
, Nicholas Sutardja, Yue Lu, Elad Alon:
Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology. IEEE J. Solid State Circuits 52(12): 3474-3485 (2017) - [c4]Jaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon:
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology. ISSCC 2017: 112-113 - 2016
- [j2]Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon:
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology. IEEE J. Solid State Circuits 51(4): 871-880 (2016) - [j1]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4): 930-942 (2016) - 2015
- [c3]Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon:
A 60Gb/s 173mW receiver frontend in 65nm CMOS technology. VLSIC 2015: 230- - [c2]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC 2015: 316- - 2013
- [c1]John Crossley, Alberto Puggelli, Hanh-Phuc Le, B. Yang, R. Nancollas, Kwangmo Jung, Lingkai Kong, Nathan Narevsky, Yue Lu, Nicholas Sutardja, E. J. An, Alberto L. Sangiovanni-Vincentelli, Elad Alon:
BAG: a designer-oriented integrated framework for the development of AMS circuit generators. ICCAD 2013: 74-81
Coauthor Index
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