"A 60Gb/s 173mW receiver frontend in 65nm CMOS technology."

Jaeduk Han et al. (2015)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2015.7231268

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/HanLSJA15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/HanLSJA15
Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon:
A 60Gb/s 173mW receiver frontend in 65nm CMOS technology. VLSIC 2015: 230-

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.