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2020 – today
- 2020
[c11]Yunsup Lee, Andrew Waterman:
Managing Chip Design Complexity in the Domain-Specific SoC Era. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c10]David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanovic:
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. FPGA 2019: 330-339 - 2017
- [c9]Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael S. Georgas, Andrew S. Waterman, Jeffrey M. Shainline, Rimas R. Avizienis, Sen Lin, Benjamin R. Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry M. Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic:
Microprocessor chip with photonic I/O. OFC 2017: 1-3 - 2016
- [b1]Andrew Waterman:
Design of the RISC-V Instruction Set Architecture. University of California, Berkeley, USA, 2016 - [j4]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4): 930-942 (2016) - [j3]Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic:
An Agile Approach to Building RISC-V Microprocessors. IEEE Micro 36(2): 8-20 (2016) - 2015
- [j2]Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael Georgas, Andrew Waterman, Jeffrey M. Shainline, Rimas Avizienis, Sen Lin, Benjamin Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic:
Single-chip microprocessor that communicates directly using light. Nat. 528(7581): 534-538 (2015) - [c8]Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic:
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium 2015: 1-45 - [c7]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC 2015: 316- - 2014
- [c6]Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovic, Krste Asanovic:
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. ESSCIRC 2014: 199-202 - 2013
- [c5]Yunsup Lee, David Sheffield, Andrew Waterman, Michael J. Anderson, Kurt Keutzer, Krste Asanovic:
Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition. Hot Chips Symposium 2013: 1-2 - [c4]Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David A. Patterson, Krste Asanovic:
The RISC-V instruction set. Hot Chips Symposium 2013: 1 - 2012
- [c3]Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic:
Chisel: constructing hardware in a Scala embedded language. DAC 2012: 1216-1225 - 2010
- [c2]Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic:
RAMP gold: an FPGA-based architecture simulator for multiprocessors. DAC 2010: 463-468 - [c1]Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson:
A case for FAME: FPGA architecture model execution. ISCA 2010: 290-301
2000 – 2009
- 2009
- [j1]Samuel Williams, Andrew Waterman, David A. Patterson:
Roofline: an insightful visual performance model for multicore architectures. Commun. ACM 52(4): 65-76 (2009)
Coauthor Index
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