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ORCIDKwanseo Park
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2020 – today
- 2024
[j26]Minkyo Shim
, Seungha Roh, Yunhee Lee, Jung-Woo Sull, Deog-Kyoon Jeong, Kwanseo Park:
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3550-3560 (2024)- [j25]Young-Ha Hwang, Kwanseo Park:
Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1844-1848 (2024) - [j24]Suil Kang, Dongwoo Kang, Sinho Lee, Minkyo Shim, Seungha Roh, Sunjin Choi, Kwanseo Park:
A 0.09-pJ/b/dB 28-Gb/s Digital CDR With ISI-Resistant Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4618-4622 (2024) - [j23]Dongwoo Kang, Han-Gon Ko, Kwanseo Park:
A 3×12 -Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4633-4637 (2024) - [c14]Zhongkai Wang, Minsoo Choi, Paul Kwon, Zhaokai Liu, Bozhi Yin, Kyoungtae Lee, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. ISCAS 2024: 1-5 - 2023
- [j22]Minkyo Shim, Woonghee Lee, Yunhee Lee, Kwanseo Park, Deog-Kyoon Jeong:
A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link. IEEE Access 11: 46513-46521 (2023) - [j21]Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong:
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS. IEEE J. Solid State Circuits 58(5): 1414-1424 (2023) - [j20]Minkyo Shim, Kwang-Hoon Lee, Seungha Roh, Kwanseo Park, Deog-Kyoon Jeong:
A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 381-385 (2023) - 2022
- [j19]Zhongkai Wang, Minsoo Choi, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. IEEE J. Solid State Circuits 57(1): 21-31 (2022) - [j18]Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong:
Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. IEEE J. Solid State Circuits 57(2): 573-585 (2022) - [j17]Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong:
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. IEEE J. Solid State Circuits 57(10): 3014-3024 (2022) - [c13]Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. VLSI Technology and Circuits 2022: 34-35 - 2021
- [j16]Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong:
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. IEEE Access 9: 156789-156798 (2021) - [j15]Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong:
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits 56(5): 1597-1607 (2021) - [j14]Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong:
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021) - [j13]Kwangho Lee, Hyojun Kim, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park, Ook Kim, Deog-Kyoon Jeong:
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 622-626 (2021) - [c12]Minsoo Choi, Zhongkai Wang, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Elad Alon:
8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS. ISSCC 2021: 128-130 - 2020
- [j12]Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong:
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference. IEEE J. Solid State Circuits 55(8): 2186-2195 (2020) - [c11]Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong:
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. ISSCC 2020: 124-126 - [c10]Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong:
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. ISSCC 2020: 128-130
2010 – 2019
- 2019
- [j11]Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong:
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE J. Solid State Circuits 54(10): 2812-2822 (2019) - [j10]Gyu-Seob Jeong, Byungjun Kang, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong:
A Modulo-FIR Equalizer for Wireline Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4278-4286 (2019) - [j9]Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim:
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1927-1931 (2019) - [j8]Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong:
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1932-1936 (2019) - [c9]Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong:
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits 2019: 194- - [c8]Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog-Kyoon Jeong:
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level. VLSI Circuits 2019: 198- - [c7]Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong:
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. VLSI Circuits 2019: 268- - 2018
- [j7]Kwanseo Park, Woo-Rham Bae, Jinhyung Lee, Jeongho Hwang, Deog-Kyoon Jeong:
A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. IEEE J. Solid State Circuits 53(10): 2982-2993 (2018) - [j6]Jinhyung Lee, Kwanseo Park, Kwangho Lee, Deog-Kyoon Jeong:
A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1295-1299 (2018) - [j5]Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1395-1399 (2018) - [j4]Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong:
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. IEEE Trans. Ind. Electron. 65(7): 5979-5989 (2018) - 2017
- [j3]Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong:
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1432-1436 (2017) - [c6]Kwanseo Park, Woo-Rham Bae, Deog-Kyoon Jeong:
A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. CICC 2017: 1-4 - 2016
- [j2]Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. IEEE J. Solid State Circuits 51(10): 2357-2367 (2016) - [j1]Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1393-1403 (2016) - [c5]Woo-Rham Bae, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong:
A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS. A-SSCC 2016: 241-244 - 2015
- [c4]Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. A-SSCC 2015: 1-4 - [c3]Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. ISCAS 2015: 2389-2392 - 2014
- [c2]Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC 2014: 447-450
2000 – 2009
- 2000
- [c1]Young Ik Son, Hyungbo Shim, Kwanseo Park, Jin Heon Seo:
Stabilization of linear systems via low-order dynamic output feedback: a passification approach. ACC 2000: 3822-3826
Coauthor Index
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