"A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS."

Kwanseo Park et al. (2015)

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DOI: 10.1109/ISCAS.2015.7169165

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-16

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  - https://dblp.org/rec/conf/iscas/ParkBJLJKJ15
Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. ISCAS 2015: 2389-2392

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