default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSubhendu Roy
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2022
[j9]Hao Geng
, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu:
High-Speed Adder Design Space Exploration via Graph Neural Processes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2657-2670 (2022)- 2021
- [j8]Urmimala Roy, Tanmoy Pramanik, Subhendu Roy, Avhishek Chatterjee, Leonard F. Register, Sanjay Kumar Banerjee:
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory. ACM Trans. Design Autom. Electr. Syst. 26(3): 24:1-24:17 (2021)
2010 – 2019
- 2019
- [j7]Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu:
Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2298-2311 (2019) - 2018
- [j6]Jin Miao, Meng Li, Subhendu Roy, Yuzhe Ma, Bei Yu:
SD-PUF: Spliced Digital Physical Unclonable Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 927-940 (2018) - [i2]Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu:
Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. CoRR abs/1807.07023 (2018) - 2017
- [c10]Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu:
A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. ISLPED 2017: 1-6 - 2016
- [j5]Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan:
Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. 59(6): 061406:1-061406:23 (2016) - [j4]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 820-831 (2016) - [j3]Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan:
OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1618-1629 (2016) - [c9]Jin Miao, Meng Li, Subhendu Roy, Bei Yu:
LRR-DPUF: learning resilient and reliable digital physical unclonable function. ICCAD 2016: 46 - 2015
- [j2]Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 589-602 (2015) - [c8]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. ASP-DAC 2015: 249-254 - [c7]Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan:
OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. DAC 2015: 129:1-129:6 - [c6]Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet:
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI 2015: 87-90 - [c5]Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen:
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. ICCD 2015: 236-243 - 2014
- [j1]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1517-1530 (2014) - [c4]Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD 2014: 69-76 - [c3]Subhendu Roy, David Z. Pan:
Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. VLSID 2014: 38-43 - [i1]Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan:
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). CoRR abs/1408.0407 (2014) - 2013
- [c2]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC 2013: 48:1-48:8 - 2010
- [c1]Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Large Scale VLSI Circuit Simulation Using Point Relaxation. CSC 2010: 343-347
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-23 19:28 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
