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ORCIDPavlos M. Mattheakis
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2020 – today
- 2020
[c9]Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos:
Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV. ISPD 2020: 25-32
2010 – 2019
- 2019
- [j4]Ioannis Seitanidis, Giorgos Dimitrakopoulos
, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1501-1514 (2019) - 2017
- [c8]Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC 2017: 56:1-56:6 - 2016
- [j3]Nikolaos Tampouratzis, Pavlos M. Mattheakis, Ioannis Papaefstathiou:
Accelerating Intercommunication in Highly Parallel Systems. ACM Trans. Archit. Code Optim. 13(4): 40:1-40:25 (2016) - [c7]Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. ACM Great Lakes Symposium on VLSI 2016: 335-340 - 2015
- [j2]Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 589-602 (2015) - [c6]Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet:
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI 2015: 87-90 - 2014
- [c5]Giorgos Dimitrakopoulos, I. Seitanidis, Anastasios Psarras, K. Tsiouris, Pavlos M. Mattheakis, Jordi Cortadella:
Hardware primitives for the synthesis of multithreaded elastic systems. DATE 2014: 1-4 - [c4]Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD 2014: 69-76 - 2013
- [b1]Pavlos M. Mattheakis:
Logic synthesis of concurrent control specifications. University of Crete, Greece, 2013 - [j1]Pavlos M. Mattheakis, Ioannis Papaefstathiou:
Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems. ACM Trans. Archit. Code Optim. 9(4): 51:1-51:25 (2013) - [c3]Pavlos M. Mattheakis, Christos P. Sotiriou:
Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition. VLSI Design 2013: 251-256 - 2012
- [c2]Pavlos M. Mattheakis, Christos P. Sotiriou, Peter A. Beerel:
A polynomial time flow for implementing free-choice Petri-nets. ICCD 2012: 227-234
2000 – 2009
- 2006
- [c1]Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou:
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. FPL 2006: 1-6
Coauthor Index
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