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ORCID24. ACM Great Lakes Symposium on VLSI 2016: Boston, MA, USA
- Ayse K. Coskun, Martin Margala, Laleh Behjat, Jie Han:
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016. ACM 2016, ISBN 978-1-4503-4274-2
Keynote 1
- Marc Witteman:
Why Is It So Hard to Make Secure Chips? 1
Keynote 2
- Yusuf Leblebici:
Design and Implementation of Real-Time Multi-sensor Vision Systems. 3
Keynote 3
- Kevin Fu:
Medical Device Security: The First 165 Years. 5
Keynote 4
- Ingrid Verbauwhede
:
VLSI Design Methods for Low Power Embedded Encryption. 7
Session 1: VLSI Circuits 1
- Chaohui Du, Guoqiang Bai, Xingjun Wu:
High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key Cryptosystems. 9-14 - Kyle Juretus, Ioannis Savidis:
Reduced Overhead Gate Level Logic Encryption. 15-20 - Salin Junsangsri, Jie Han, Fabrizio Lombardi:
A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File. 21-26 - Xiaolin Xu, Daniel E. Holcomb:
A Clockless Sequential PUF with Autonomous Majority Voting. 27-32
Session 2: VLSI and Test
- Bo Yuan, Yanzhi Wang, Zhongfeng Wang:
Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing. 33-38 - Pei Luo, Cheng Li, Yunsi Fei:
Concurrent Error Detection for Reliable SHA-3 Design. 39-44 - Travis Boraten, Dominic DiTomaso, Avinash Karanth Kodi:
Secure Model Checkers for Network-on-Chip (NoC) Architectures. 45-50 - Sita Kondamadugula, Srinath R. Naidu:
Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield Optimization. 51-56
Session 3: VLSI Design 1
- Amey M. Kulkarni, Tahmid Abtahi, Emily Smith, Tinoosh Mohsenin:
Low Energy Sketching Engines on Many-Core Platform for Big Data Acceleration. 57-62 - Adam Page, Nasrin Attaran, Colin Shea, Houman Homayoun, Tinoosh Mohsenin:
Low-Power Manycore Accelerator for Personalized Biomedical Applications. 63-68 - Jaya Dofe, Qiaoyan Yu, Hailang Wang, Emre Salman:
Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs. 69-74 - Qin Xiong, Zhonghai Lu, Fei Wu, Changsheng Xie:
Real-Time Analysis for Wormhole NoC: Revisited and Revised. 75-80
Session 4: CAD 1
- Yu-Hsiang Hung, Sheng-Hsin Fang, Hung-Ming Chen, Shen-Min Chen, Chang-Tzu Lin, Chia-Hsin Lee:
A New Methodology for Noise Sensor Placement Based on Association Rule Mining. 81-86 - Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu:
MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. 87-92 - Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He, Yuchun Ma:
Modular Placement for Interposer based Multi-FPGA Systems. 93-98 - Zhezhao Xu, Wenjian Yu, Chao Zhang, Bolong Zhang, Meijuan Lu, Michael Mascagni:
A Parallel Random Walk Solver for the Capacitance Calculation Problem in Touchscreen Design. 99-104
Poster Session 1
- Chen Yang, Yan Li, Wei Zhong, Song Chen:
Real-Time Hardware Stereo Matching Using Guided Image Filter. 105-108 - Yin Liu, Keshab K. Parhi:
Computing Complex Functions using Factorization in Unipolar Stochastic Logic. 109-112 - Mohsen Imani, Shruti Patil, Tajana Simunic Rosing:
DCC: Double Capacity Cache Architecture for Narrow-Width Values. 113-116 - Nidhi Batra, Pawan Sehgal, Shashwat Kaushik, Mohammad S. Hashmi, Sudesh Bhalla, Anuj Grover:
Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques. 117-120 - Aditya Dalakoti, Carrie Segal, Merritt Miller, Forrest Brewer:
Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event Detection. 121-124 - Wei Wei, Kazuteru Namba, Fabrizio Lombardi:
Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level. 125-128 - Daniel Prashanth, Hae-Seung Lee:
A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs. 129-132 - Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu:
Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. 133-136 - Md Farhadur Reza, Dan Zhao, Hongyi Wu:
Task-Resource Co-Allocation for Hotspot Minimization in Heterogeneous Many-Core NoCs. 137-140 - Hamed Tabkhi, Majid Sabbagh, Gunar Schirner:
Guiding Power/Quality Exploration for Communication-Intense Stream Processing. 141-144
Session 5: Low Power 1
- Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. 145-150 - Govinda Sannena, Bishnu Prasad Das:
A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance. 151-156 - Tosiron Adegbija:
Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems. 157-162 - Jaeyoung Park, Michael Orshansky:
Multiple Attempt Write Strategy for Low Energy STT-RAM. 163-168
Special Session 1: IoT Security: Issues, Innovations and Interplays
- Md Tanvir Arafin, Gang Qu:
Secret Sharing and Multi-user Authentication: From Visual Cryptography to RRAM Circuits. 169-174 - Doug Palmer, Saverio Fazzari, Scott Wartenberg:
Defense Systems and IoT: Security Issues in an Era of Distributed Command and Control. 175-179 - Garrett S. Rose:
Security Meets Nanoelectronics for Internet of Things Applications. 181-183 - Thao Le, Jia Di, Mark M. Tehranipoor, Domenic Forte, Lei Wang:
Tracking Data Flow at Gate-Level through Structural Checking. 185-189
Session 6: Test 2
- Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson:
Design of Error-Resilient Logic Gates with Reinforcement Using Implications. 191-196 - Sparsh Mittal, Jeffrey S. Vetter:
Reducing Soft-error Vulnerability of Caches using Data Compression. 197-202 - Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. 203-208 - Ralph Nyberg, Johann Heyszl, Dietmar Heinz, Georg Sigl:
Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault Propagation. 209-214
Session 7: VLSI Circuits 2
- Yongsuk Choi, Yong-Bin Kim:
A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC. 215-219 - Rui Zhou, Weikang Qian:
A General Sign Bit Error Correction Scheme for Approximate Adders. 221-226 - Amr M. S. Tosson, Mohab H. Anis, Lan Wei:
RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO2/Hf 1T1R RRAM Memory Cell. 227-232 - Ravi Patel, Kan Xu, Eby G. Friedman, Praveen Raghavan:
Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs. 233-238 - Amr M. S. Tosson Abdelwahed, Adam Neale, Mohab H. Anis, Lan Wei:
8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design. 239-244
Session 8: Emerging 1
- Naman Saraf, Kia Bazargan:
Polynomial Arithmetic Using Sequential Stochastic Logic. 245-250 - Yu Bai, Bo Hu, Weidong Kuang, Mingjie Lin:
Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices. 251-256 - Ioannis A. Papistas, Vasilis F. Pavlidis:
Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects. 257-262 - Subrata Das, Soma Das, Adrija Majumder, Parthasarathi Dasgupta, Debesh Kumar Das:
Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees. 263-268
Session 9: CAD 2
- Pietro Mercati, Francesco Paterna, Andrea Bartolini, Mohsen Imani, Luca Benini, Tajana Simunic Rosing:
VarDroid: Online Variability Emulation in Android/Linux Platforms. 269-274 - Ning Liu, Caiwen Ding, Yanzhi Wang, Jingtong Hu:
Neural Network-based Prediction Algorithms for In-Door Multi-Source Energy Harvesting System for Non-Volatile Processors. 275-280 - Sara Vinco, Yukai Chen, Enrico Macii, Massimo Poncino:
A Unified Model of Power Sources for the Simulation of Electrical Energy Systems. 281-286 - Munish Jassi, Uzair Sharif, Daniel Müller-Gritschneder, Ulf Schlichtmann:
Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs. 287-292 - Vincent Mirian, Paul Chow:
Extracting Designs of Secure IPs Using FPGA CAD Tools. 293-298
Special Session 3: Emerging Technology Devices and Security
- Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia:
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. 299-304 - Yu Bi, Xiaobo Sharon Hu, Yier Jin, Michael T. Niemier, Kaveh Shamsi, Xunzhao Yin:
Enhancing Hardware Security with Emerging Transistor Technologies. 305-310 - Chaofei Yang, Beiye Liu, Yandan Wang, Yiran Chen, Hai Li, Xian Zhang, Guangyu Sun:
The Applications of NVM Technology in Hardware Security. 311-316 - Ilia A. Bautista Adames, Jayita Das, Sanjukta Bhanja:
Survey of Emerging Technology Based Physical Unclonable Funtions. 317-322
Session 10: VLSI Design 2
- Yong Chen, Emil Matús, Gerhard P. Fettweis:
Trellis-search based Dynamic Multi-Path Connection Allocation for TDM-NoCs. 323-328 - Morteza Soltani, Mohammad Ebrahimi, Zainalabedin Navabi:
Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping. 329-334 - Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. 335-340 - Marcelo Ruaro, Fernando Gehm Moraes:
Dynamic Real-Time Scheduler for Large-Scale MPSoCs. 341-346
Special Session 4: Emerging Frontiers in Hardware Security
- Peng Gu, Shuangchen Li, Dylan C. Stow, Russell Barnes, Liu Liu, Yuan Xie, Eren Kursun:
Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. 347-352
Poster Session 2
- Jiachen Song, Xi Li, Beilei Sun, Zhinan Cheng, Chao Wang, Xuehai Zhou:
FCM: Towards Fine-Grained GPU Power Management for Closed Source Mobile Games. 353-356 - Mohamad Hammam Alsafrjalani, Ann Gordon-Ross:
Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded Devices. 357-360 - Saman Kiamehr, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Temperature-aware Dynamic Voltage Scaling for Near-Threshold Computing. 361-364 - Tuhin Subhra Chakraborty, Santanu Kundu, Deepak Agrawal, Sanjay Tanaji Shinde, Jacob Mathews, Rekha K. James:
Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths. 365-368 - Adam Watkins, Spyros Tragoudas:
An Enhanced Analytical Electrical Masking Model for Multiple Event Transients. 369-372 - Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic:
Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. 373-376 - Vijeta Rathore, Vivek Chaturvedi, Thambipillai Srikanthan:
Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore Systems. 377-380 - Jordi Perez-Puigdemont, Francesc Moll:
ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation System. 381-384 - Deliang Fan:
Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate. 385-388 - Hang Zhang, Xuhao Chen, Nong Xiao, Fang Liu, Zhiguang Chen:
Red-Shield: Shielding Read Disturbance for STT-RAM Based Register Files on GPUs. 389-392 - Poorna Marthi, Sheikh Rufsan Reza, Nazir Hossain, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González:
Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits. 393-396
Session 11: Emerging 2
- Qingda Hu, Guangyu Sun, Jiwu Shu, Chao Zhang:
Exploring Main Memory Design Based on Racetrack Memory Technology. 397-402 - Ali Alsuwaiyan, Kartik Mohanram:
An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories. 403-408 - Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices. 409-414 - Hassan Afzali-Kusha, Alireza Shafaei, Massoud Pedram:
Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry. 415-420
Session 12: Low Power 2
- Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino:
Approximate Differential Encoding for Energy-Efficient Serial Communication. 421-426 - Yukai Chen, Sara Vinco, Enrico Macii, Massimo Poncino:
Fast Thermal Simulation using SystemC-AMS. 427-432 - Cosimo Aprile, Luca Baldassarre, Vipul Gupta, Juhwan Yoo, Mahsa Shoaran, Yusuf Leblebici, Volkan Cevher:
Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition. 433-438 - Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis:
Load Balanced On-Chip Power Delivery for Average Current Demand. 439-444
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