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ORCIDSrinath R. Naidu
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2020 – today
- 2024
[j3]Srinath R. Naidu, Gopalakrishnan Venkiteswaran:
Optimal oversampling ratio in two-step simulation. Monte Carlo Methods Appl. 30(3): 281-297 (2024)
2010 – 2019
- 2018
- [c9]Pinkey Kumari, Srinath R. Naidu:
Fast Approach for Iris Detection on GPU by Applying Search Localization for Circular Hough Transform. ICACCI 2018: 774-778 - 2016
- [c8]Sita Kondamadugula
, Srinath R. Naidu:
Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield Optimization. ACM Great Lakes Symposium on VLSI 2016: 51-56 - [c7]Sita Kondamadugula, Srinath R. Naidu:
Accelerated evolutionary algorithms with parameterimportance based population initialization for variation-aware analog yield optimization. MWSCAS 2016: 1-4 - 2015
- [c6]Srinath R. Naidu:
Geometric Programming Formulation for Gate Sizing with Pipelining Constraints. VLSID 2015: 452-457
2000 – 2009
- 2007
- [c5]A. Nardi, Emre Tuncer, Srinath R. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song:
Use of statistical timing analysis on real designs. DATE 2007: 1605-1610 - [c4]Srinath R. Naidu:
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits. VLSI Design 2007: 265-270 - 2006
- [j2]Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah:
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2376-2392 (2006) - 2003
- [j1]Srinath R. Naidu, Vijay Chandru:
On Synthesis of Easily Testable (k, K) Circuits. IEEE Trans. Computers 52(11): 1490-1494 (2003) - [c3]Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah:
Statistical timing for parametric yield prediction of digital integrated circuits. DAC 2003: 932-937 - 2002
- [c2]Srinath R. Naidu:
Timing Yield Calculation Using an Impulse-Train Approach. ASP-DAC/VLSI Design 2002: 219-224 - 2001
- [c1]Srinath R. Naidu, E. T. A. F. Jacobs:
Minimizing stand-by leakage power in static CMOS circuits. DATE 2001: 370-376
Coauthor Index
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