"Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of ..."

Srinath R. Naidu (2007)

> Home

Details and statistics

DOI: 10.1109/VLSID.2007.147

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/Naidu07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/Naidu07
Srinath R. Naidu:
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits. VLSI Design 2007: 265-270

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.