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ORCIDJochen A. G. Jess
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2000 – 2009
- 2006
[j13]Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu
, Ralph H. J. M. Otten, Chandramouli Visweswariah:
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2376-2392 (2006)- 2003
- [j12]Jochen A. G. Jess:
Codeübersetzung unter Zeitvorgaben für eingebettete Signalprozessoren (Performance Controlled Compilation for Embedded Signal Processors). it Inf. Technol. 45(6): 327-335 (2003) - [c40]Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah:
Statistical timing for parametric yield prediction of digital integrated circuits. DAC 2003: 932-937 - 2002
- [c39]Jochen A. G. Jess:
Parametric Yield Estimation for Deep Sub- Micron VLSI Circuits. SBCCI 2002: 387 - 2001
- [c38]Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess:
Constraint satisfaction for storage files with Fifos or stacks during scheduling. DATE 2001: 824 - [c37]Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess:
Constraint Satisfaction for Relative Location Assignment and Scheduling. ICCAD 2001: 384-390 - [c36]Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen:
Phase coupled operation assignment for VLIW processors with distributed register files. ISSS 2001: 118-123 - [c35]Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess:
Static resource models of instruction sets. ISSS 2001: 159-164 - 2000
- [j11]Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
Prophid: A Platform-Based Design Method. Des. Autom. Embed. Syst. 6(1): 5-37 (2000) - [j10]Jochen A. G. Jess:
Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itself. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12): 1404-1427 (2000) - [j9]Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess:
A code-motion pruning technique for global scheduling. ACM Trans. Design Autom. Electr. Syst. 5(1): 1-38 (2000) - [j8]Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess:
Constraint analysis for code generation: basic techniques and applications in FACTS. ACM Trans. Design Autom. Electr. Syst. 5(4): 774-793 (2000) - [c34]Carlos A. Alba Pinto, Koen van Eijk, Bart Mesman, Jochen A. G. Jess:
Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP Algorithms. SBCCI 2000: 107-112 - [c33]Qin Zhao, C. A. J. van Eijk, Carlos A. Alba Pinto, Jochen A. G. Jess:
Register Binding for Predicated Execution in DSP Applications. SBCCI 2000: 113-118
1990 – 1999
- 1999
- [j7]Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
Constraint analysis for DSP code generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(1): 44-57 (1999) - [c32]Luiz C. V. dos Santos, Jochen A. G. Jess:
A Reordering Technique for Efficient Code Motion. DAC 1999: 296-299 - [c31]Luiz C. V. dos Santos, Jochen A. G. Jess:
Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation. DATE 1999: 609- - 1998
- [c30]Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. DATE 1998: 125-131 - [c29]Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
A Constraint Driven Approach to Loop Pipelining and Register Binding. DATE 1998: 377-383 - 1997
- [c28]Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
PROPHID: a data-driven multi-processor architecture for high-performance DSP. ED&TC 1997: 611 - [c27]Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. ICCD 1997: 164-169 - [c26]Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
Constraint Analysis for DSP Code Generation. ISSS 1997: 33-40 - 1996
- [j6]Chennian Di, Jochen A. G. Jess:
An efficient CMOS bridging fault simulator: with SPICE accuracy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1071-1080 (1996) - [j5]Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess:
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1424-1434 (1996) - [c25]C. A. J. van Eijk, Jochen A. G. Jess:
Exploiting Functional Dependencies in Finite State Machine Verification. ED&TC 1996: 9-14 - [c24]Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess:
A Constructive Method for Exploiting Code Motion. ISSS 1996: 51-56 - 1995
- [c23]Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess:
High-level synthesis scheduling and allocation using genetic algorithms. ASP-DAC 1995 - [c22]Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess:
Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. DAC 1995: 593-598 - [c21]Adwin H. Timmer, Jochen A. G. Jess:
Exact scheduling strategies based on bipartite graph matching. ED&TC 1995: 42-47 - [c20]J. W. G. Fleurkens, C. A. J. van Eijk, Jochen A. G. Jess:
Run-time consistency checking in discrete simulation models. ED&TC 1995: 223-227 - [c19]Marino T. J. Strik, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess, Stefaan Note:
Efficient code generation for in-house DSP-cores. ED&TC 1995: 244-251 - [c18]Jeroen A. J. Leijten, Jef L. van Meerbergen, Jochen A. G. Jess:
Analysis and reduction of glitches in synchronous networks. ED&TC 1995: 398-403 - 1994
- [c17]Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess:
Routing for Manufacturability. DAC 1994: 402-406 - [c16]Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess:
On Design Rule Correct Maze Routing. EDAC-ETC-EUROASIC 1994: 407-411 - [c15]Hua Xue, Chennian Di, Jochen A. G. Jess:
Probability Analysis for CMOS Floating Gate Faults. EDAC-ETC-EUROASIC 1994: 443-448 - [c14]Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess:
Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. ICCAD 1994: 474-480 - [c13]M. J. M. Heijiligers, H. A. Hilderink, Adwin H. Timmer, Jochen A. G. Jess:
NEAT: An Object Oriented High-Level Synthesis Interface. ISCAS 1994: 233-236 - [e4]Jochen A. G. Jess, Richard L. Rudell:
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994. IEEE Computer Society / ACM 1994, ISBN 0-89791-690-5 [contents] - 1993
- [j4]Ed P. Huijbregts, Jochen A. G. Jess:
General gate array routing using a k-terminal net routing algorithm with failure prediction. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 473-481 (1993) - [c12]Hua Xue, Chennian Di, Jochen A. G. Jess:
Fast Multi-Layer Critical Area Computation. DFT 1993: 117-124 - [c11]Hua Xue, Chennian Di, Jochen A. G. Jess:
A net-oriented method for realistic fault analysis. ICCAD 1993: 78-83 - [c10]Adwin H. Timmer, Jochen A. G. Jess:
Execution interval analysis under resource constraints. ICCAD 1993: 454-459 - [c9]M. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess:
Parameter Monitoring: Advantages and Pitfalls. ITC 1993: 115-124 - [c8]Chennian Di, Jochen A. G. Jess:
On Accurate Modeling and Efficient Simulation of CMOS Opens. ITC 1993: 875-882 - [c7]Ed P. Huijbregts, Jochen A. G. Jess:
A Multiple Terminal Net Routing Algorithm Using Failure Prediction. VLSI Design 1993: 84-89 - [c6]Chennian Di, Jochen A. G. Jess:
On CMOS bridge fault modeling and test pattern evaluation. VTS 1993: 116-119 - [e3]Michael R. Lightner, Jochen A. G. Jess:
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993. IEEE Computer Society / ACM 1993, ISBN 0-8186-4490-7 [contents] - 1992
- [j3]Leon Stok, Jochen A. G. Jess:
Foreground memory management in data path synthesis. Int. J. Circuit Theory Appl. 20(3): 235-255 (1992) - 1991
- [c5]Eric Bruls, F. Camerik, H. J. Kretschman, Jochen A. G. Jess:
A Generic Method to Develop a Defect Monitoring System for IC Processes. ITC 1991: 218-227 - [e2]Tony Ambler, Jochen A. G. Jess, Hugo De Man:
Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991. EEE Computer Society 1991, ISBN 0-8186-2130-3 [contents] - 1990
- [c4]Michel R. C. M. Berkelaar, Jochen A. G. Jess:
Gate sizing in MOS digital circuits with linear programming. EURO-DAC 1990: 217-221 - [e1]Gordon Adshead, Jochen A. G. Jess:
European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990. IEEE Computer Society 1990, ISBN 0-8186-2024-2 [contents]
1980 – 1989
- 1989
- [j2]José Pineda de Gyvez, Jochen A. G. Jess:
On the design and implementation of a wafer yield editor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(8): 920-925 (1989) - [c3]José Pineda de Gyvez, Jochen A. G. Jess:
A layout defect-sensitivity extractor. ICCAD 1989: 538-541 - [c2]F. Camerik, P. A. J. Dirks, Jochen A. G. Jess:
Qualification and Quantification of Process-Induced Product-Related Defects. ITC 1989: 643-652 - 1988
- [c1]Michel R. C. M. Berkelaar, Jochen A. G. Jess:
Technology mapping for standard-cell generators. ICCAD 1988: 470-473 - 1982
- [j1]Jochen A. G. Jess, H. G. M. Kees:
A Data Structure for Parallel L/U Decomposition. IEEE Trans. Computers 31(3): 231-239 (1982)
Coauthor Index
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