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ORCIDMichel R. C. M. Berkelaar
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2000 – 2009
- 2004
[c13]Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz:
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. ICCD 2004: 350-353- [c12]Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz:
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. MBMV 2004: 24-33 - 2002
- [c11]Michel R. C. M. Berkelaar, Koen van Eijk:
Efficient and Effective Redundancy Removal for Million-Gate Circuits. DATE 2002: 1088 - 2000
- [c10]E. T. A. F. Jacobs, Michel R. C. M. Berkelaar:
Gate Sizing Using a Statistical Delay Model. DATE 2000: 283-290
1990 – 1999
- 1998
- [j2]Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk:
Computing observability don't cares efficiently through polarization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(7): 573-581 (1998) - [c9]J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren:
An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization. DATE 1998: 749-754 - [c8]J. W. J. M. Rutten, Michel R. C. M. Berkelaar:
Efficient exact and heuristic minimization of hazard-free logic. ICCD 1998: 152-159 - 1997
- [c7]J. W. J. M. Rutten, Michel R. C. M. Berkelaar:
Improved State Assignment for Burst Mode Finite State Machines. ASYNC 1997: 228-239 - 1996
- [j1]Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess:
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1424-1434 (1996) - [c6]Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk:
Polarized observability don't cares. ICCAD 1996: 626-631 - 1995
- [c5]Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken:
Efficient orthonormality testing for synthesis with pass-transistor selectors. ICCAD 1995: 256-263 - [c4]Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash:
Efficient use of large don't cares in high-level and logic synthesis. ICCAD 1995: 272-278 - 1994
- [c3]Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess:
Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. ICCAD 1994: 474-480 - 1990
- [c2]Michel R. C. M. Berkelaar, Jochen A. G. Jess:
Gate sizing in MOS digital circuits with linear programming. EURO-DAC 1990: 217-221
1980 – 1989
- 1988
- [c1]Michel R. C. M. Berkelaar, Jochen A. G. Jess:
Technology mapping for standard-cell generators. ICCAD 1988: 470-473
Coauthor Index
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