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ORCID3rd ASYNC 1997: Eindhoven, The Netherlands
- 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands. IEEE Computer Society 1997, ISBN 0-8186-7922-0
Pipelines and Meshes
- D. A. Gilbert, Jim D. Garside:
A Result Forwarding Mechanism for Asynchronous Pipelined Systems. 2-11 - Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt
:
Two-Phase Asynchronous Pipeline Control. 12-23 - O. A. Petlin, Stephen B. Furber:
Built-In Self-Testing of Micropipelines. 22-29 - Peggy B. K. Pang, Mark R. Greenstreet:
Self-Timed Meshes Are Faster Than Synchronous. 30-
Exotic Implementations
- Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell:
Delay Insensitive Logic for RSFQ Superconductor Technology. 42-53 - Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni:
On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. 54-
Performance Analysis
- Aiguo Xie, Peter A. Beerel:
Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events. 64-75 - Jo C. Ebergen, Robert Berks:
Response Time Properties of Some Asynchronous Circuits. 76-
Timing Analysis
- Wendy Belluomini, Chris J. Myers:
Efficient Timing Analysis Algorithms for Timed State Space Exploration. 88-100 - Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun:
Timing Analysis of Extended Burst-Mode Circuits. 101-111 - Supratik Chakraborty, David L. Dill:
More Accurate Polynomial-Time Min-Max Timing Simulation. 112-
Design
- Pedro A. Molina, Peter Y. K. Cheung:
A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. 126-139 - Kenneth Y. Yun, Ayoob E. Dooply, Julio Arceo, Peter A. Beerel, Vida Vakilotojar:
The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver. 140-
Formal Methods
- Juha Plosila, Kaisa Sere:
Action Systems in Pipelined Processor Design. 156-166 - Paul G. Lucassen, Indra Polak, Jan Tijmen Udding:
Normal Form in DI-Algebra with Recursion. 167-174 - Willem C. Mallon, Jan Tijmen Udding:
Using Metrics for Proof Rules for Recursively Defined Delay-insensitive Specifications. 175-
Arithmetic
- David A. Kearney, Neil W. Bergmann:
Bundled Data Asynchronous Multipliers with Data Dependent Computation Times. 186-197 - Gensoh Matsubara, Nobuhiro Ide:
A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit. 198-209 - Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel:
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. 210-
Synthesis
- J. W. J. M. Rutten, Michel R. C. M. Berkelaar:
Improved State Assignment for Burst Mode Finite State Machines. 228-239 - Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev:
Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. 240-253 - Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, Luciano Lavagno:
Partial order based approach to synthesis of speed-independent circuits. 254-
Silicon
- Joep L. W. Kessels, Paul Marston:
Designing Asynchronous Standby Circuits for a Low-Power Pager. 268-278 - Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau:
A FIFO Ring Performance Experiment. 279-289 - Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver:
AMULET2e: An Asynchronous Embedded Controller. 290-
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