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ORCIDGarrett S. Rose
Garrett Steven Rose
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- affiliation: University of Tennessee, Knoxville, USA
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2020 – today
- 2024
[j37]Nishith N. Chakraborty
, Shelah Ameli, Hritom Das, Catherine D. Schuman, Garrett S. Rose:
Hardware software co-design for leveraging STDP in a memristive neuroprocessor. Neuromorph. Comput. Eng. 4(2): 24010 (2024)- [c103]Manu Rathore, Garrett S. Rose:
AnSpiCS-Net: Reconfigurable Network-on-Chip for Analog Spiking Recurrent Neural Networks. ISCAS 2024: 1-5 - [c102]SNB Tushar, Hritom Das, Garrett S. Rose:
HfO2-Based Synaptic Spiking Neural Network Evaluation to Optimize Design and Testing Cost. ISCAS 2024: 1-5 - [c101]Hritom Das, Imran Fahad, SNB Tushar, Sk Hasibul Alam, Graham Buchanan, Danny Scott, Garrett S. Rose, Sai Swaminathan:
In-Sensor Motion Recognition with Memristive System and Light Sensing Surfaces. ISVLSI 2024: 192-197 - [c100]Catherine D. Schuman, Hritom Das, Garrett S. Rose, James S. Plank:
Evaluation of Neuron Parameters on the Performance of Spiking Neural Networks and Neuromorphic Hardware. ISVLSI 2024: 337-342 - [c99]Hritom Das, Nishith N. Chakraborty, Manu Rathore, Sk Hasibul Alam, Catherine D. Schuman, Garrett S. Rose:
A Memristive Reconfigurable Neuromorphic Array for Neuro-Inspired Dynamic Architectures. ISVLSI 2024: 415-420 - [c98]Hritom Das, Karan P. Patel, Shelah Ameli, Nishith N. Chakraborty, Catherine D. Schuman, Garrett S. Rose:
Hardware-Application Co-Design to Evaluate the Performance of an STDP-based Reservoir Computer. ISVLSI 2024: 666-670 - [c97]Manu Rathore, Garrett S. Rose:
Maximizing Efficiency of SNN-Based Reservoir Computing via NoC-Assisted Dimensionality Reduction. ISVLSI 2024: 671-674 - [c96]Garrett S. Rose, Tosiron Adegbija, Selçuk Köse:
Message from the Technical Program Chairs; ISVLSI 2024. ISVLSI 2024: xxviii-xxix - [c95]Manu Rathore, Garrett S. Rose:
Leveraging Sparsity of SRNNs for Reconfigurable and Resource-Efficient Network-on-Chip. NICE 2024: 1-8 - [c94]Catherine D. Schuman, Charles P. Rizzo, Garrett S. Rose, James S. Plank:
Embracing the Hairball: An Investigation of Recurrence in Spiking Neural Networks for Control. NICE 2024: 1-5 - [c93]Manu Rathore, Garrett S. Rose:
SpiCS-Net: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural Networks. VLSID 2024: 204-209 - 2023
- [j36]Mst Shamim Ara Shawkat, Md Musabbir Adnan, Rocco D. Febbo, John J. Murray, Garrett S. Rose:
A Single Chip SPAD Based Vision Sensing System With Integrated Memristive Spiking Neuromorphic Processing. IEEE Access 11: 19441-19457 (2023) - [j35]Hritom Das, Rocco D. Febbo, Charles P. Rizzo, Nishith N. Chakraborty, James S. Plank, Garrett S. Rose:
Optimizations for a Current-Controlled Memristor- Based Neuromorphic Synapse Design. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 889-900 (2023) - [j34]Hritom Das, Rocco D. Febbo, Sree Nirmillo Biswash Tushar, Nishith N. Chakraborty, Maximilian Liehr, Nathaniel C. Cady, Garrett S. Rose:
An Efficient and Accurate Memristive Memory for Array-Based Spiking Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4804-4815 (2023) - [c92]Catherine D. Schuman, Hritom Das, James S. Plank, Ahmedullah Aziz, Garrett S. Rose:
Evaluating Neuron Models through Application-Hardware Co-Design. ACSSC 2023: 537-542 - [c91]Manu Rathore, Rocco D. Febbo, Adam Z. Foshie, Sree Nirmillo Biswash Tushar, Hritom Das, Garrett S. Rose:
Reliability Analysis of Memristive Reservoir Computing Architecture. ACM Great Lakes Symposium on VLSI 2023: 131-136 - [c90]Nishith N. Chakraborty, Hritom Das, Garrett S. Rose:
A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse. ACM Great Lakes Symposium on VLSI 2023: 179-182 - [c89]Sk Hasibul Alam, Adam Z. Foshie, Garrett S. Rose:
A Runtime-Reconfigurable Hardware Encoder for Spiking Neural Networks. ACM Great Lakes Symposium on VLSI 2023: 203-206 - [c88]Hritom Das, Manu Rathore, Rocco Febbo, Maximilian Liehr, Nathaniel C. Cady, Garrett S. Rose:
RFAM: RESET-Failure-Aware-Model for HfO2-based Memristor to Enhance the Reliability of Neuromorphic Design. ACM Great Lakes Symposium on VLSI 2023: 281-286 - [c87]Shelah Ameli, Adam Z. Foshie, Drew Friend, James S. Plank, Garrett S. Rose, Catherine D. Schuman:
Algorithm and Application Impacts of Programmable Plasticity in Spiking Neuromorphic Hardware. ICONS 2023: 39:1-39:6 - [c86]Nishith N. Chakraborty, Hritom Das, Garrett S. Rose:
Spike-Timing-Dependent Plasticity for a Hafnium-Oxide Memristive Synapse. MWSCAS 2023: 463-467 - [c85]Nishith N. Chakraborty, Hritom Das, Garrett S. Rose:
Spike-Driven Synaptic Plasticity for a Memristive Neuromorphic Core. MWSCAS 2023: 644-648 - [c84]Nishith N. Chakraborty, Hritom Das, Garrett S. Rose:
Homeostatic Plasticity in a Leaky Integrate and Fire Neuron Using Tunable Leak. MWSCAS 2023: 738-742 - [c83]Nishith N. Chakraborty, SNB Tushar, Hritom Das, Garrett S. Rose:
Energy Efficient and High-Performance Synaptic Operating Point Evaluation for SNN Applications. MWSCAS 2023: 918-922 - [i13]Hritom Das, Rocco D. Febbo, Charles Rizzo, Nishith N. Chakraborty, James S. Plank, Garrett S. Rose:
Optimizations for a Current-Controlled Memristor-based Neuromorphic Synapse Design. CoRR abs/2305.16418 (2023) - [i12]Hritom Das, Rocco D. Febbo, Sree Nirmillo Biswash Tushar, Nishith N. Chakraborty, Maximilian Liehr, Nathaniel C. Cady, Garrett S. Rose:
An Efficient and Accurate Memristive Memory for Array-based Spiking Neural Networks. CoRR abs/2306.06551 (2023) - [i11]Hritom Das, Nishith N. Chakraborty, Catherine D. Schuman, Garrett S. Rose:
Enhanced Read Resolution in Reconfigurable Memristive Synapses for Spiking Neural Networks. CoRR abs/2306.13721 (2023) - [i10]Adam Z. Foshie, James S. Plank, Garrett S. Rose, Catherine D. Schuman:
Functional Specification of the RAVENS Neuroprocessor. CoRR abs/2307.15232 (2023) - [i9]Md. Mazharul Islam, Shamiul Alam, Mohammad Adnan Jahangir, Garrett S. Rose, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta, Ahmedullah Aziz:
Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing. CoRR abs/2308.15756 (2023) - [i8]Md Sakib Hasan, Catherine D. Schuman, Zhongyang Zhang, Tauhidur Rahman, Garrett S. Rose:
Spike-based Neuromorphic Computing for Next-Generation Computer Vision. CoRR abs/2310.09692 (2023) - 2022
- [j33]Jack Hutchins, Shamiul Alam, Andre Zeumault, Karsten Beckmann, Nathaniel C. Cady, Garrett S. Rose, Ahmedullah Aziz:
A Generalized Workflow for Creating Machine Learning-Powered Compact Models for Multi-State Devices. IEEE Access 10: 115513-115519 (2022) - [j32]Saraju P. Mohanty, Jim Plusquellic, Garrett S. Rose, Wei Zhang, Maria K. Michael:
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things. ACM J. Emerg. Technol. Comput. Syst. 18(1): 1:1-1:3 (2022) - [j31]Bon Woong Ku, Catherine D. Schuman, Md Musabbir Adnan, Tiffany M. Mintz, Raphael C. Pooser, Kathleen E. Hamilton, Garrett S. Rose, Sung Kyu Lim:
Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System. ACM J. Emerg. Technol. Comput. Syst. 18(2): 38:1-38:20 (2022) - [c82]Adam Z. Foshie, Charles Rizzo, Hritom Das, Chaohui Zheng, James S. Plank, Garrett S. Rose:
Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control Applications. ACM Great Lakes Symposium on VLSI 2022: 383-386 - [c81]Nishith N. Chakraborty, Garrett S. Rose, Min H. Kao:
Programmable Refractory Period Implementations in a Mixed-Signal Integrate-And-Fire Neuron. ISCAS 2022: 770-774 - [c80]Shamiul Alam, Md. Mazharul Islam, Akhilesh Jaiswal, Nathaniel C. Cady, Garrett S. Rose, Ahmedullah Aziz:
Variation-aware Design Space Exploration of Mott Memristor-based Neuristors. ISVLSI 2022: 68-73 - [c79]Md Musabbir Adnan, Mst Shamim Ara Shawkat, Rocco D. Febbo, Garrett S. Rose:
On-Chip Interface for Event based Sensor and Spiking Neuromorphic Processing. MWSCAS 2022: 1-4 - [c78]Manu Rathore, Ryan Weiss, Mst Shamim Ara Shawkat, Garrett S. Rose, Maximilian Liehr, Minhaz Abedin, Sarah Rafiq, Nathaniel C. Cady:
A Compact Model for the Variable Switching Dynamics of HfO2 Memristors. MWSCAS 2022: 1-4 - [c77]Ryan Weiss, Hritom Das, Nishith N. Chakraborty, Garrett S. Rose:
STDP Based Online Learning for a Current-Controlled Memristive Synapse. MWSCAS 2022: 1-4 - [c76]Catherine D. Schuman, James S. Plank, Robert M. Patton, Thomas E. Potok, Garrett S. Rose:
A Framework to Enable Top-Down Co-Design of Neuromorphic Systems for Real-World Applications. NICE 2022: 84-85 - [i7]James S. Plank, Chaohui Zheng, Bryson Gullett, Nicholas D. Skuda, Charles Rizzo, Catherine D. Schuman, Garrett S. Rose:
The Case for RISP: A Reduced Instruction Spiking Processor. CoRR abs/2206.14016 (2022) - [i6]James S. Plank, Bryson Gullett, Adam Z. Foshie, Garrett S. Rose, Catherine D. Schuman:
Disclosure of a Neuromorphic Starter Kit. CoRR abs/2211.04526 (2022) - 2021
- [j30]Md Musabbir Adnan, Sagarvarma Sayyaparaju, Samuel D. Brown, Mst Shamim Ara Shawkat, Catherine D. Schuman, Garrett S. Rose:
Design of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware. ACM J. Emerg. Technol. Comput. Syst. 17(4): 56:1-56:26 (2021) - [j29]Garrett S. Rose, Mst Shamim Ara Shawkat, Adam Z. Foshie, John J. Murray, Md Musabbir Adnan:
A system design perspective on neuromorphic computer processors. Neuromorph. Comput. Eng. 1(2): 22001 (2021) - [j28]Aysha S. Shanta, Md. Badruddoja Majumder, Md Sakib Hasan, Garrett S. Rose:
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 405-418 (2021) - [c75]Adam Z. Foshie, Nishith N. Chakraborty, John J. Murray, Tanner J. Fowler, Mst Shamim Ara Shawkat, Garrett S. Rose:
A Multi-Context Neural Core Design for Reconfigurable Neuromorphic Arrays. ISVLSI 2021: 67-72 - [c74]John J. Murray, Adam Z. Foshie, Mst Shamim Ara Shawkat, Garrett S. Rose:
Scaling Constraints for Memristor-based Programmable Interconnect in Reconfigurable Computing Arrays. ISVLSI 2021: 102-107 - [c73]Samuel D. Brown, Md Musabbir Adnan, Mst Shamim Ara Shawkat, Garrett S. Rose:
Capacitor-Less Memristive Integrate-and-Fire Neuron with Stochastic Behavior. MWSCAS 2021: 175-178 - [e1]Thomas E. Potok, Melika Payvand, Catherine D. Schuman, Prasanna Date, Mutsumi Kimura, Cory E. Merkel, Brad Aimone, Sonia M. Buckley, Yiran Chen, Gregory Cohen, Todd Hylton, Robert M. Patton, Robinson E. Pino, Garrett S. Rose:
ICONS 2021: International Conference on Neuromorphic Systems 2021, Knoxville, TN, USA, July 27-29, 2021. ACM 2021, ISBN 978-1-4503-8691-3 [contents] - [i5]Md Sakib Hasan, Aysha S. Shanta, Partha Sarathi Paul, Maisha Sadia, Md. Badruddoja Majumder, Garrett S. Rose:
Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map. CoRR abs/2101.00334 (2021) - 2020
- [j27]Karsten Beckmann, Wilkie Olin-Ammentorp, Gangotree Chakma, Sherif Amer, Garrett S. Rose, Chris Hobbs, Joseph Van Nostrand, Martin Rodgers, Nathaniel C. Cady:
Towards Synaptic Behavior of Nanoscale ReRAM Devices for Neuromorphic Computing Applications. ACM J. Emerg. Technol. Comput. Syst. 16(2): 23:1-23:18 (2020) - [j26]Sagarvarma Sayyaparaju, Md Musabbir Adnan, Sherif Amer, Garrett S. Rose:
Device-aware Circuit Design for Robust Memristive Neuromorphic Systems with STDP-based Learning. ACM J. Emerg. Technol. Comput. Syst. 16(3): 28:1-28:25 (2020) - [j25]Md Sakib Hasan, Md. Badruddoja Majumder, Aysha S. Shanta, Mesbah Uddin, Garrett S. Rose:
A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering. J. Hardw. Syst. Secur. 4(2): 69-85 (2020) - [c72]Jonathan D. Ambrose, Adam Z. Foshie, Mark E. Dean, James S. Plank, Garrett S. Rose, J. Parker Mitchell, Catherine D. Schuman, Grant Bruer:
GRANT: Ground-Roaming Autonomous Neuromorphic Targeter. IJCNN 2020: 1-8 - [c71]Catherine D. Schuman, J. Parker Mitchell, Maryam Parsa, James S. Plank, Samuel D. Brown, Garrett S. Rose, Robert M. Patton, Thomas E. Potok:
Automated Design of Neuromorphic Networks for Scientific Applications at the Edge. IJCNN 2020: 1-7 - [c70]Aaron R. Young, Adam Z. Foshie, Mark E. Dean, James S. Plank, Garrett S. Rose, J. Parker Mitchell, Catherine D. Schuman:
Scaled-up Neuromorphic Array Communications Controller (SNACC) for Large-scale Neural Networks. IJCNN 2020: 1-8 - [c69]Sagarvarma Sayyaparaju, Mst Shamim Ara Shawkat, Md Musabbir Adnan, Garrett S. Rose:
Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing. ISCAS 2020: 1-5 - [c68]Mst Shamim Ara Shawkat, Sagarvarma Sayyarparaju, Nicole McFarlane, Garrett S. Rose:
Single Photon Avalanche Diode based Vision Sensor with On-Chip Memristive Spiking Neuromorphic Processing. MWSCAS 2020: 377-380 - [i4]Mesbah Uddin, Md. Badruddoja Majumder, Md Sakib Hasan, Garrett S. Rose:
A Secure Back-up and Restore for Resource-Constrained IoT based on Nanotechnology. CoRR abs/2007.04570 (2020)
2010 – 2019
- 2019
- [j24]Aaron R. Young, Mark E. Dean, James S. Plank, Garrett S. Rose:
A Review of Spiking Neuromorphic Hardware Communication Systems. IEEE Access 7: 135606-135620 (2019) - [j23]Md. Badruddoja Majumder, Md Sakib Hasan, Mesbah Uddin, Garrett S. Rose:
A Secure Integrity Checking System for Nanoelectronic Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 416-429 (2019) - [c67]Mesbah Uddin, Md Sakib Hasan, Garrett S. Rose:
On the Theoretical Analysis of Memristor based True Random Number Generator. ACM Great Lakes Symposium on VLSI 2019: 21-26 - [c66]Md. Badruddoja Majumder, Md Sakib Hasan, Aysha S. Shanta, Mesbah Uddin, Garrett S. Rose:
Design for Eliminating Operation Specific Power Signatures from Digital Logic. ACM Great Lakes Symposium on VLSI 2019: 111-116 - [c65]Mesbah Uddin, Aysha S. Shanta, Md. Badruddoja Majumder, Md Sakib Hasan, Garrett S. Rose:
Memristor Crossbar PUF based Lightweight Hardware Security for IoT. ICCE 2019: 1-4 - [c64]Samuel D. Brown, Gangotree Chakma, Md Musabbir Adnan, Md Sakib Hasan, Garrett S. Rose:
Stochasticity in Neuromorphic Computing: Evaluating Randomness for Improved Performance. ICECS 2019: 454-457 - [c63]Md Musabbir Adnan, Sherif Amer, Sagarvarma Sayyaparaju, Md Sakib Hasan, Garrett S. Rose:
A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory. ICECS 2019: 630-633 - [c62]Maximilian Liehr, Jubin Hazra, Karsten Beckmann, Wilkie Olin-Ammentorp, Nathaniel C. Cady, Ryan Weiss, Sagarvarma Sayyaparaju, Garrett S. Rose, Joseph Van Nostrand:
Fabrication and Performance of Hybrid ReRAM-CMOS Circuit Elements for Dynamic Neural Networks. ICONS 2019: 6:1-6:4 - [c61]Sherif Amer, Garrett S. Rose:
A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar Arrays. ISQED 2019: 64-69 - [c60]Aysha S. Shanta, Md Sakib Hasan, Md. Badruddoja Majumder, Garrett S. Rose:
Design of a Lightweight Reconfigurable PRNG Using Three Transistor Chaotic Map. MWSCAS 2019: 586-589 - [c59]Sherif Amer, Md Sakib Hasan, Md Musabbir Adnan, Garrett S. Rose:
Design Considerations for Insulator Metal Transition based Artificial Neurons. MWSCAS 2019: 1131-1134 - 2018
- [j22]Mesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose:
Nanoelectronic Security Designs for Resource-Constrained Internet of Things Devices: Finding Security Solutions with Nanoelectronic Hardwares. IEEE Consumer Electron. Mag. 7(6): 15-22 (2018) - [j21]Jeremy Liu, Federico M. Spedalieri, Ke-Thia Yao, Thomas E. Potok, Catherine D. Schuman, Steven R. Young, Robert M. Patton, Garrett S. Rose, Gangotree Chakma:
Adiabatic Quantum Computation Applied to Deep Learning Networks. Entropy 20(5): 380 (2018) - [j20]Gangotree Chakma, Md Musabbir Adnan, Austin Wyer, Ryan Weiss, Catherine D. Schuman, Garrett S. Rose:
Memristive Mixed-Signal Neuromorphic Systems: Energy-Efficient Learning at the Circuit-Level. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 125-136 (2018) - [j19]Daniel Brown, Ava Hedayatipour, Md. Badruddoja Majumder, Garrett S. Rose, Nicole McFarlane, Donatello Materassi:
Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry. IET Comput. Digit. Tech. 12(6): 297-305 (2018) - [j18]Mesbah Uddin, Md. Badruddoja Majumder, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady, Garrett S. Rose:
Design Considerations for Memristive Crossbar Physical Unclonable Functions. ACM J. Emerg. Technol. Comput. Syst. 14(1): 2:1-2:23 (2018) - [j17]Thomas E. Potok, Catherine D. Schuman, Steven R. Young, Robert M. Patton, Federico M. Spedalieri, Jeremy Liu, Ke-Thia Yao, Garrett S. Rose, Gangotree Chakma:
A Study of Complex Deep Learning Networks on High-Performance, Neuromorphic, and Quantum Computers. ACM J. Emerg. Technol. Comput. Syst. 14(2): 19:1-19:21 (2018) - [c58]Ryan Weiss, Joseph S. Najem, Md Sakib Hasan, Catherine D. Schuman, Alex Belianinov, C. Patrick Collier, Stephen A. Sarles, Garrett S. Rose:
A Soft-Matter Biomolecular Memristor Synapse for Neuromorphic Systems. BioCAS 2018: 1-4 - [c57]Gangotree Chakma, Nicholas D. Skuda, Catherine D. Schuman, James S. Plank, Mark E. Dean, Garrett S. Rose:
Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices. ACM Great Lakes Symposium on VLSI 2018: 379-383 - [c56]Md. Badruddoja Majumder, Md Sakib Hasan, Mesbah Uddin, Garrett S. Rose:
Chaos computing for mitigating side channel attack. HOST 2018: 143-146 - [c55]Aaron R. Young, Mark E. Dean, James S. Plank, Garrett S. Rose, Catherine D. Schuman:
Neuromorphic Array Communications Controller to Support Large-Scale Neural Networks. IJCNN 2018: 1-8 - [c54]Md Musabbir Adnan, Sherif Amer, Garrett S. Rose:
A Novel Scan-In Scheme for CMOS/ReRAM Programmable Logic Circuits. ISCAS 2018: 1-5 - [c53]Nicholas D. Skuda, Catherine D. Schuman, Gangotree Chakma, James S. Plank, Garrett S. Rose:
High-Level Simulation for Spiking Neuromorphic Computing Systems. ISCAS 2018: 1-5 - [c52]Sagarvarma Sayyaparaju, Sherif Amer, Garrett S. Rose:
A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems. ISQED 2018: 69-74 - [c51]Sagarvarma Sayyaparaju, Ryan Weiss, Garrett S. Rose:
A Mixed-Mode Neuron with On-chip Tunability for Generic Use in Memristive Neuromorphic Systems. ISVLSI 2018: 441-446 - [c50]Aysha S. Shanta, Md. Badruddoja Majumder, Md Sakib Hasan, Mesbah Uddin, Garrett S. Rose:
Design of a Reconfigurable Chaos Gate with Enhanced Functionality Space in 65nm CMOS. MWSCAS 2018: 1016-1019 - [c49]Md Musabbir Adnan, Sagarvarma Sayyaparaju, Garrett S. Rose, Catherine D. Schuman, Bon Woong Ku, Sung Kyu Lim:
A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems. SoCC 2018: 37-42 - [c48]Mesbah Uddin, Garrett S. Rose:
A Practical Sense Amplifier Design for Memristive Crossbar Circuits (PUF). SoCC 2018: 209-214 - 2017
- [c47]Sagarvarma Sayyaparaju, Gangotree Chakma, Sherif Amer, Garrett S. Rose:
Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems. ACM Great Lakes Symposium on VLSI 2017: 479-482 - [c46]James S. Plank, Garrett S. Rose, Mark E. Dean, Catherine D. Schuman, Nathaniel C. Cady:
A Unified Hardware/Software Co-Design Framework for Neuromorphic Computing Devices and Applications. ICRC 2017: 1-8 - [c45]Sherif Amer, Sagarvarma Sayyaparaju, Garrett S. Rose, Karsten Beckmann, Nathaniel C. Cady:
A practical hafnium-oxide memristor model suitable for circuit design and simulation. ISCAS 2017: 1-4 - [c44]Garrett S. Rose, Md. Badruddoja Majumder, Mesbah Uddin:
Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices. ISVLSI 2017: 615-620 - [c43]Ryan Weiss, Gangotree Chakma, Garrett S. Rose:
A synchronized axon hillock neuron for memristive neuromorphic systems. MWSCAS 2017: 361-364 - [c42]Gangotree Chakma, Sagarvarma Sayyaparaju, Ryan Weiss, Garrett S. Rose:
A mixed-signal approach to memristive neuromorphic system design. MWSCAS 2017: 547-550 - [c41]Sherif Amer, Garrett S. Rose, Karsten Beckmann, Nathaniel C. Cady:
Design techniques for in-field memristor forming circuits. MWSCAS 2017: 1224-1227 - [c40]Catherine D. Schuman, James S. Plank, Garrett S. Rose, Gangotree Chakma, Austin Wyer, Grant Bruer, Nouamane Laanait:
A programming framework for neuromorphic systems with emerging technologies. NANOCOM 2017: 15:1-15:7 - [c39]Catherine D. Schuman, Thomas E. Potok, Steven R. Young, Robert M. Patton, Gabriel N. Perdue, Gangotree Chakma, Austin Wyer, Garrett S. Rose:
Neuromorphic computing for temporal scientific data classification. NCS 2017: 2:1-2:6 - [c38]Austin Wyer, Md Musabbir Adnan, Bon Woong Ku, Sung Kyu Lim, Catherine D. Schuman, Raphael C. Pooser, Garrett S. Rose:
Evaluating online-learning in memristive neuromorphic circuits. NCS 2017: 5:1-5:8 - [i3]Thomas E. Potok, Catherine D. Schuman, Steven R. Young, Robert M. Patton, Federico M. Spedalieri, Jeremy Liu, Ke-Thia Yao, Garrett S. Rose, Gangotree Chakma:
A Study of Complex Deep Learning Networks on High Performance, Neuromorphic, and Quantum Computers. CoRR abs/1703.05364 (2017) - [i2]Catherine D. Schuman, Thomas E. Potok, Robert M. Patton, J. Douglas Birdwell, Mark E. Dean, Garrett S. Rose, James S. Plank:
A Survey of Neuromorphic Computing and Neural Networks in Hardware. CoRR abs/1705.06963 (2017) - 2016
- [c37]Garrett S. Rose:
Security Meets Nanoelectronics for Internet of Things Applications. ACM Great Lakes Symposium on VLSI 2016: 181-183 - [c36]Md. Badruddoja Majumder, Mesbah Uddin, Garrett S. Rose, Jeyavijayan Rajendran:
Sneak path enabled authentication for memristive crossbar memories. AsianHOST 2016: 1-6 - [c35]Mark E. Dean, Jason Chan, Christopher Daffron, Adam Disney, John Reynolds, Garrett S. Rose, James S. Plank, J. Douglas Birdwell, Catherine D. Schuman:
An Application Development Platform for neuromorphic computing. IJCNN 2016: 1347-1354 - [c34]Garrett S. Rose, Mesbah Uddin, Md. Badruddoja Majumder:
A Designer's Rationale for Nanoelectronic Hardware Security Primitives. ISVLSI 2016: 194-199 - [c33]Mesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady:
Techniques for Improved Reliability in Memristive Crossbar PUF Circuits. ISVLSI 2016: 212-217 - [c32]Thomas E. Potok, Catherine D. Schuman, Steven R. Young, Robert M. Patton, Federico M. Spedalieri, Jeremy Liu, Ke-Thia Yao, Garrett S. Rose, Gangotree Chakma:
A Study of Complex Deep Learning Networks on High Performance, Neuromorphic, and Quantum Computers. MLHPC@SC 2016: 47-55 - 2015
- [j16]Jeyavijayan Rajendran, Ramesh Karri, James B. Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki:
Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications. Proc. IEEE 103(5): 829-849 (2015) - [j15]Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Fault Analysis-Based Logic Encryption. IEEE Trans. Computers 64(2): 410-424 (2015) - [j14]Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose:
Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors. IEEE Trans. Computers 64(3): 733-746 (2015) - [c31]Garrett S. Rose, Chauncey A. Meade:
Performance analysis of a memristive crossbar PUF design. DAC 2015: 75:1-75:6 - [c30]James Bohl, Lok-Kwong Yan, Garrett S. Rose:
A two-dimensional chaotic logic gate for improved computer security. MWSCAS 2015: 1-4 - 2014
- [j13]Miao Hu, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose, Richard W. Linderman:
Memristor Crossbar-Based Neuromorphic Computing System: A Case Study. IEEE Trans. Neural Networks Learn. Syst. 25(10): 1864-1878 (2014) - [c29]Garrett Steven Rose:
A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation. ISVLSI 2014: 54-58 - [c28]Dhireesha Kudithipudi, Cory E. Merkel, Yu Kee Ooi, Qutaiba Saleh, Garrett S. Rose:
On designing circuit primitives for cortical processors with memristive hardware. SoCC 2014: 371-376 - [p3]Dhireesha Kudithipudi, Cory E. Merkel, Michael Soltiz, Garrett S. Rose, Robinson E. Pino:
Design of Neuromorphic Architectures with Memristors. Network Science and Cybersecurity 2014: 93-103 - [p2]Garrett S. Rose, Dhireesha Kudithipudi, Ganesh Khedkar, Nathan R. McDonald, Bryant T. Wysocki, Lok-Kwong Yan:
Nanoelectronics and Hardware Security. Network Science and Cybersecurity 2014: 105-123 - [p1]Bryant T. Wysocki, Nathan R. McDonald, Clare Thiem, Garrett S. Rose, Mario Gomez II:
Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments. Network Science and Cybersecurity 2014: 137-153 - 2013
- [j12]Michael Soltiz, Dhireesha Kudithipudi, Cory E. Merkel, Garrett S. Rose, Robinson E. Pino:
Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions. IEEE Trans. Computers 62(8): 1597-1606 (2013) - [c27]Garrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki:
Hardware security strategies exploiting nanoelectronic circuits. ASP-DAC 2013: 368-372 - [c26]Miao Hu, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose:
BSB training scheme implementation on memristor-based circuit. CISDA 2013: 80-87 - [c25]Garrett S. Rose, Nathan R. McDonald, Lok-Kwong Yan, Bryant T. Wysocki:
A write-time based memristive PUF for hardware security applications. ICCAD 2013: 830-833 - [c24]Garrett S. Rose, Nathan R. McDonald, Lok-Kwong Yan, Bryant T. Wysocki, Karen Xu:
Foundations of memristor based PUF architectures. NANOARCH 2013: 52-57 - 2012
- [j11]Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose:
Design Considerations for Multilevel CMOS/Nano Memristive Memory. ACM J. Emerg. Technol. Comput. Syst. 8(1): 6:1-6:22 (2012) - [j10]Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino:
Leveraging Memristive Systems in the Construction of Digital Logic Circuits. Proc. IEEE 100(6): 2033-2049 (2012) - [j9]Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose:
An Energy-Efficient Memristive Threshold Logic Circuit. IEEE Trans. Computers 61(4): 474-487 (2012) - [j8]Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose:
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(5): 1051-1060 (2012) - [c23]Miao Hu, Hai Li, Qing Wu, Garrett S. Rose:
Hardware realization of BSB recall function using memristor crossbar arrays. DAC 2012: 498-503 - [c22]Miao Hu, Hai Li, Qing Wu, Garrett S. Rose, Yiran Chen:
Memristor crossbar based hardware realization of BSB recall function. IJCNN 2012: 1-7 - [c21]Jeyavijayan Rajendran, Garrett S. Rose, Ramesh Karri, Miodrag Potkonjak:
Nano-PPUF: A Memristor-Based Security Primitive. ISVLSI 2012: 84-87 - [c20]Michael Soltiz, Cory E. Merkel, Dhireesha Kudithipudi, Garrett S. Rose:
RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layer. NANOARCH 2012: 218-225 - [c19]Garrett S. Rose:
Exploiting memristive device behavior for emerging digital logic and memory applications. SoCC 2012: 292 - [i1]Jeyavijayan Rajendran, Ramesh Karri, James B. Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki:
Nanoelectronic Solutions for Hardware Security. IACR Cryptol. ePrint Arch. 2012: 575 (2012) - 2011
- [j7]Shamik Das, Garrett S. Rose:
Introduction to Special Issue: Highlights of NANOARCH'09. ACM J. Emerg. Technol. Comput. Syst. 7(1): 1:1-1:2 (2011) - [j6]Aamir Zia, Sachhidh Kannan, H. Jonathan Chao, Garrett S. Rose:
3D NOC for many-core processors. Microelectron. J. 42(12): 1380-1390 (2011) - [c18]Garrett S. Rose, Robinson E. Pino, Qing Wu:
A low-power memristive neuromorphic circuit utilizing a global/local training mechanism. IJCNN 2011: 2080-2086 - [c17]Sachhidh Kannan, Garrett S. Rose:
A hierarchical 3-D floorplanning algorithm for many-core CMP networks. ISCAS 2011: 1211-1214 - [c16]Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose:
Parallel memristors: Improving variation tolerance in memristive digital circuits. ISCAS 2011: 2241-2244 - [c15]Harika Manem, Garrett S. Rose:
A read-monitored write circuit for 1T1M multi-level memristor memories. ISCAS 2011: 2938-2941 - [c14]Garrett S. Rose, Robinson E. Pino, Qing Wu:
Exploiting memristance for low-energy neuromorphic computing hardware. ISCAS 2011: 2942-2945 - [c13]Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose:
An Approach to Tolerate Process Related Variations in Memristor-Based Applications. VLSI Design 2011: 18-23 - 2010
- [c12]Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang:
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory. ACM Great Lakes Symposium on VLSI 2010: 287-292 - [c11]Garrett S. Rose:
Overview: Memristive devices, circuits and systems. ISCAS 2010: 1955-1958 - [c10]Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose:
Memristor based programmable threshold logic array. NANOARCH 2010: 5-10
2000 – 2009
- 2009
- [j5]Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon:
Inversion schemes for sublithographic programmable logic arrays. IET Comput. Digit. Tech. 3(6): 625-642 (2009) - [c9]Harika Manem, Garrett S. Rose:
The effects of logic partitioning in a majority logic based CMOS-NANO FPGA. ACM Great Lakes Symposium on VLSI 2009: 157-160 - [c8]Yongji Jiang, Garrett S. Rose:
A dual-MOSFET equivalent resistor thermal sensor. ACM Great Lakes Symposium on VLSI 2009: 181-184 - [c7]Xiaofei Guo, Shunting Lin, Wael Refai, Garrett S. Rose:
Non-overlapping transition encoding for global on-chip interconnect. SoCC 2009: 255-258 - 2008
- [c6]Harika Manem, Peter C. Paliwoda, Garrett S. Rose:
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays. ACM Great Lakes Symposium on VLSI 2008: 249-254 - 2007
- [j4]Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan:
Designing CMOS/molecular memories while considering device parameter variations. ACM J. Emerg. Technol. Comput. Syst. 3(1): 3 (2007) - [j3]Garrett S. Rose, Mircea R. Stan:
A Programmable Majority Logic Array Using Molecular Scale Electronics. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2380-2390 (2007) - [j2]Shamik Das, Alexander J. Gates, Hassen A. Abdu, Garrett S. Rose, Carl A. Picconatto, James C. Ellenbogen:
Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2528-2540 (2007) - [c5]Nadine Gergel-Hackett, Garrett S. Rose, Peter C. Paliwoda, Christina A. Hacker, Curt A. Richter:
On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results. ACM Great Lakes Symposium on VLSI 2007: 108-113 - 2006
- [c4]Garrett S. Rose, Mircea R. Stan:
A programmable majority logic array using molecular scale electronics. FPGA 2006: 225 - [c3]Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour:
Design approaches for hybrid CMOS/molecular memory based on experimental device data. ACM Great Lakes Symposium on VLSI 2006: 2-7 - [c2]Zhenyu Qi, Wei Huang, Adam C. Cabe, Wenqian Wu, Yan Zhang, Garrett S. Rose, Mircea R. Stan:
A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors. SoCC 2006: 111-112 - [c1]Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler:
Hybrid CMOS/Molecular Electronic Circuits. VLSI Design 2006: 703-708 - 2004
- [j1]Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan:
Large-signal two-terminal device model for nanoelectronic circuit analysis. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1201-1208 (2004)
Coauthor Index
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