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2010 – 2019
- 2018
[j6]Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). ACM Trans. Reconfigurable Technol. Syst. 11(1): 3:1-3:23 (2018)- 2017
- [j5]Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon
:
Self-Adaptive Timing Repair. IEEE Des. Test 34(6): 54-62 (2017) - [c9]Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. FPGA 2017: 85-94 - 2016
- [c8]Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). FCCM 2016: 111-118 - [c7]Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, André DeHon:
Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement. FPGA 2016: 100-104 - 2015
- [j4]Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon:
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction. ACM Trans. Reconfigurable Technol. Syst. 7(4): 32:1-32:23 (2015) - 2014
- [c6]Benjamin Gojman, André DeHon:
GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction. FCCM 2014: 88-95 - 2013
- [c5]Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon:
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction. FPGA 2013: 81-90 - 2011
- [j3]André DeHon, Benjamin Gojman:
Crystals and Snowflakes: Building Computation from Nanowire Crossbars. Computer 44(2): 37-45 (2011) - [p1]Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon:
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 381-432
2000 – 2009
- 2009
- [j2]Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon:
Inversion schemes for sublithographic programmable logic arrays. IET Comput. Digit. Tech. 3(6): 625-642 (2009) - [c4]Benjamin Gojman, André DeHon:
VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems. FPT 2009: 78-87 - 2006
- [c3]Benjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto:
3D Nanowire-Based Programmable Logic. Nano-Net 2006: 1-5 - 2005
- [j1]Benjamin Gojman, Eric Rachlin, John E. Savage:
Evaluation of design strategies for stochastically assembled nanoarray memories. ACM J. Emerg. Technol. Comput. Syst. 1(2): 73-108 (2005) - [c2]Eric Rachlin, John E. Savage, Benjamin Gojman:
Analysis of a Mask-Based Nanowire Decoder. ISVLSI 2005: 6-13 - 2004
- [c1]Benjamin Gojman, Eric Rachlin, John E. Savage:
Decoding of Stochastically Assembled Nanoarrays. ISVLSI 2004: 11-18
Coauthor Index
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