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ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 7
Volume 7, Number 1, February 2014
- George Kornaros
, Dionisios N. Pnevmatikatos:
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs. 1:1-1:26 - Yousef Iskander, Cameron D. Patterson, Stephen D. Craven:
High-Level Abstractions and Modular Debugging for FPGA Design Validation. 2:1-2:22 - Minxi Jin, Tsutomu Maruyama:
Fast and Accurate Stereo Vision System on FPGA. 3:1-3:24 - Onur Ulusel, Kumud Nepal, R. Iris Bahar, Sherief Reda:
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. 4:1-4:22 - Lok-Won Kim, Sameh W. Asaad, Ralph Linsker:
A Fully Pipelined FPGA Architecture of a Factored Restricted Boltzmann Machine Artificial Neural Network. 5:1-5:23
Volume 7, Number 2, June 2014
- Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
VTR 7.0: Next Generation Architecture and CAD System for FPGAs. 6:1-6:30 - Soumya J., Ashish Sharma, Santanu Chattopadhyay:
Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration. 7:1-7:24 - Yuanwu Lei, Lei Guo, Yong Dou, Sheng Ma, Jinbo Xu:
FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function. 8:1-8:21 - Juan Antonio Clemente, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto:
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms. 9:1-9:27 - Anh-Tuan Hoang, Takeshi Fujino:
Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA. 10:1-10:19 - Tobias Becker:
Introduction to the TRETS Special Section on the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS'12). 11:1-11:2 - Jacopo Panerati, Martina Maggio, Matteo Carminati, Filippo Sironi, Marco Triverio, Marco D. Santambrogio:
Coordination of Independent Loops in Self-Adaptive Systems. 12:1-12:16 - Andreas Agne, Markus Happe, Achim Lösch, Christian Plessl, Marco Platzner:
Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores. 13:1-13:18 - Christian Beckhoff, Dirk Koch, Jim Tørresen:
Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs. 14:1-14:23 - Xinyu Niu, Qiwei Jin, Wayne Luk, Stephen Weston:
A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in Reconfigurable Systems. 15:1-15:19
Volume 7, Number 3, August 2014
- Charles Eric LaForest, Zimo Li, Tristan O'rourke, Ming G. Liu, J. Gregory Steffan:
Composing Multi-Ported Memories on FPGAs. 16:1-16:23 - Yuanxi Peng, Manuel Saldaña, Christopher A. Madill, Xiaofeng Zou, Paul Chow:
Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications. 17:1-17:23 - Jason Helge Anderson, Kiyoung Choi:
Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12). 18:1-18:2 - Hui Yan Cheah, Fredrik Brosser, Suhaib A. Fahmy, Douglas L. Maskell:
The iDEA DSP Block-Based Soft Processor for FPGAs. 19:1-19:23 - Mohamed S. Abdelfattah, Vaughn Betz:
Networks-on-Chip for FPGAs: Hard, Soft or Mixed? 20:1-20:22 - Liang Chen, Tulika Mitra:
Graph Minor Approach for Application Mapping on CGRAs. 21:1-21:25 - Changmoo Kim, Moo-Kyoung Chung, Yeon-Gon Cho, Mario Konijnenburg, Soojung Ryu, Jeongwook Kim:
ULP-SRP: Ultra Low-Power Samsung Reconfigurable Processor for Biomedical Applications. 22:1-22:15 - Nikolaos S. Voros, Guy Gogniat:
Introduction to the Special Issue on the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'12). 23:1 - Christian Brugger, Dominic Hillenbrand, Matthias Norbert Balzer:
RIVER: Reconfigurable Flow and Fabric for Real-Time Signal Processing on FPGAs. 24:1-24:16 - Fábio P. Itturriet, Gabriel L. Nazar, Ronaldo Rodrigues Ferreira, Álvaro Freitas Moreira, Luigi Carro:
Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems. 25:1-25:17 - Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan:
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration. 26:1-26:15 - Sébastien Guillet, Florent de Lamotte, Nicolas Le Griguer, Éric Rutten, Guy Gogniat, Jean-Philippe Diguet:
Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling. 27:1-27:17
Volume 7, Number 4, January 2015
- Jon T. Butler, Tsutomu Sasao:
High-Speed Hardware Partition Generation. 28:1-28:17 - Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso:
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. 29:1-29:20 - Udit Dhawan, André DeHon:
Area-Efficient Near-Associative Memories on FPGAs. 30:1-30:22 - Daniel Llamocca, Marios S. Pattichis:
Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing. 31:1-31:30 - Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon:
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction. 32:1-32:23 - Atabak Mahram, Martin C. Herbordt:
NCBI BLASTP on High-Performance Reconfigurable Computing Systems. 33:1-33:20 - Pawel Swierczynski, Amir Moradi, David F. Oswald, Christof Paar:
Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs. 34:1-34:23 - Jo Vliegen, Nele Mentens, Ingrid Verbauwhede:
Secure, Remote, Dynamic Reconfiguration of FPGAs. 35:1-35:19 - Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk:
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. 36:1-36:17 - Bailey Miller, Frank Vahid, Tony Givargis, Philip Brisk:
Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation. 37:1-37:22
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