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2020 – today
- 2020
[j4]Dhwani Mehta, Hangwei Lu
, Olivia P. Paradis, Mukhil Azhagan Mallaiyan Sathiaseelan, M. Tanjidur Rahman, Yousef Iskander, Praveen Chawla, Damon L. Woodard, Mark M. Tehranipoor, Navid Asadizanjani:
The Big Hack Explained: Detection and Prevention of PCB Supply Chain Implants. ACM J. Emerg. Technol. Comput. Syst. 16(4): 42:1-42:25 (2020)- [j3]Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor:
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation. ACM Trans. Design Autom. Electr. Syst. 25(3): 26:1-26:27 (2020)
2010 – 2019
- 2019
- [p1]Alif Ahmed, Farimah Farahmandi, Yousef Iskander, Prabhat Mishra:
Security and Trust Verification of IoT SoCs. Security and Fault Tolerance in Internet of Things 2019: 1-19 - 2018
- [j2]Domenic Forte, Yousef Iskander:
Guest Editorial: Hardware Reverse Engineering and Obfuscation. J. Hardw. Syst. Secur. 2(4): 287-288 (2018) - [c5]Alif Ahmed, Farimah Farahmandi, Yousef Iskander, Prabhat Mishra:
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution. ITC 2018: 1-10 - 2014
- [j1]Yousef Iskander, Cameron D. Patterson, Stephen D. Craven:
High-Level Abstractions and Modular Debugging for FPGA Design Validation. ACM Trans. Reconfigurable Technol. Syst. 7(1): 2:1-2:22 (2014) - 2011
- [c4]Yousef Iskander, Cameron D. Patterson, Stephen D. Craven:
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug. FPL 2011: 518-523 - 2010
- [c3]Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tony Frangieh, Yousef Iskander, Stephen D. Craven, Cameron D. Patterson:
Accelerating FPGA development through the automatic parallel application of standard implementation tools. FPT 2010: 53-60 - [c2]Yousef Iskander, Stephen D. Craven, Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tannous Frangieh, Cameron D. Patterson:
Using partial reconfiguration and high-level models to accelerate FPGA design validation. FPT 2010: 341-344 - [c1]Tannous Frangieh, Athira Chandrasekharan, Sureshwar Rajagopalan, Yousef Iskander, Stephen D. Craven, Cameron D. Patterson:
PATIS: Using partial configuration to improve static FPGA design productivity. IPDPS Workshops 2010: 1-8
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