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ORCIDAdib Nahiyan
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2020 – today
- 2021
[j6]M. Sazadur Rahman
, Adib Nahiyan, Fahim Rahman, Saverio Fazzari, Kenneth Plaks, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor:
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks. ACM Trans. Design Autom. Electr. Syst. 26(4): 29:1-29:27 (2021)- 2020
- [j5]Huanyu Wang, Qihang Shi, Adib Nahiyan, Domenic Forte, Mark M. Tehranipoor:
A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2152-2165 (2020) - [j4]Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor:
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation. ACM Trans. Design Autom. Electr. Syst. 25(3): 26:1-26:27 (2020) - [j3]Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte, Mark M. Tehranipoor:
Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation. ACM Trans. Design Autom. Electr. Syst. 25(4): 35:1-35:22 (2020) - [c7]Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, Mark M. Tehranipoor:
SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment. VTS 2020: 1-6
2010 – 2019
- 2019
- [j2]Adib Nahiyan, Farimah Farahmandi, Prabhat Mishra, Domenic Forte, Mark M. Tehranipoor:
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1003-1016 (2019) - [c6]Adam Duncan, Grant Skipper, Andrew Stern, Adib Nahiyan, Fahim Rahman, Andrew Lukefahr, Mark M. Tehranipoor, Martin Swany:
FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection. HOST 2019: 81-90 - [c5]Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark M. Tehranipoor:
RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level. VTS 2019: 1-6 - [i3]Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark M. Tehranipoor:
RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level. CoRR abs/1901.05909 (2019) - [i2]M. Sazadur Rahman, Adib Nahiyan, Sarah Amir, Fahim Rahman, Farimah Farahmandi, Domenic Forte, Mark M. Tehranipoor:
Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design. IACR Cryptol. ePrint Arch. 2019: 946 (2019) - 2018
- [i1]Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor:
Hardware Trojan Detection through Information Flow Security Verification. CoRR abs/1803.04102 (2018) - 2017
- [c4]Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark M. Tehranipoor:
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs. ASP-DAC 2017: 617-622 - [c3]Animesh Chhotaray, Adib Nahiyan, Thomas Shrimpton, Domenic Forte, Mark M. Tehranipoor:
Standardizing Bad Cryptographic Practice: A Teardown of the IEEE Standard for Protecting Electronic-design Intellectual Property. CCS 2017: 1533-1546 - [c2]Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor:
Hardware trojan detection through information flow security verification. ITC 2017: 1-10 - 2016
- [j1]Kan Xiao, Adib Nahiyan, Mark M. Tehranipoor:
Security Rule Checking in IC Design. Computer 49(8): 54-61 (2016) - [c1]Adib Nahiyan, Kan Xiao, Kun Yang, Yier Jin, Domenic Forte, Mark M. Tehranipoor:
AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs. DAC 2016: 89:1-89:6
Coauthor Index
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