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2020 – today
- 2024
[i1]Andrei Beinarovich, Sergey Stepanov, Alexander Zaslavsky:
Optimization of Discrete Parameters Using the Adaptive Gradient Method and Directed Evolution. CoRR abs/2401.06834 (2024)
2010 – 2019
- 2018
- [j3]Marco Donato
, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 643-656 (2018) - 2016
- [c11]Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A fast simulator for the analysis of sub-threshold thermal noise transients. DAC 2016: 56:1-56:6 - [c10]Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson:
Design of Error-Resilient Logic Gates with Reinforcement Using Implications. ACM Great Lakes Symposium on VLSI 2016: 191-196 - 2015
- [c9]Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits. ACM Great Lakes Symposium on VLSI 2015: 45-50 - 2012
- [c8]Jing Wan, Cyrille Le Royer, Alexander Zaslavsky, Sorin Cristoloveanu:
Z2-FET used as 1-transistor high-speed DRAM. ESSDERC 2012: 197-200 - [c7]Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy:
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. ACM Great Lakes Symposium on VLSI 2012: 39-44 - 2010
- [c6]Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. ACM Great Lakes Symposium on VLSI 2010: 281-286
2000 – 2009
- 2007
- [j2]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electron. Test. 23(2-3): 255-266 (2007) - [c5]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE 2007: 576-581 - [c4]Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar:
Thermally-induced soft errors in nanoscale CMOS circuits. NANOARCH 2007: 62-69 - 2006
- [j1]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26(5): 19-27 (2006) - [c3]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing MRF based error correcting circuits for memory elements. DATE 2006: 792-793 - [c2]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI 2006: 149-152 - 2005
- [c1]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing logic circuits for probabilistic computation in the presence of noise. DAC 2005: 485-490
Coauthor Index
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