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2020 – today
- 2024
[j23]Pinghui Wang
, Dongdong Xie, Junzhou Zhao, Jinsong Li, Zhicheng Li, Rundong Li, Yang Ren, Jia Di:
Half-Xor: A Fully-Dynamic Sketch for Estimating the Number of Distinct Values in Big Tables. IEEE Trans. Knowl. Data Eng. 36(7): 3111-3125 (2024)- [c47]Tasnuva Farheen, Sourav Roy, Andrew Cannon, Jia Di, Shahin Tajik, Domenic Forte:
Amnesiac Memory: A Self-Destructive Polymorphic Mechanism Against Cold Boot Data Remanence Attack. ACM Great Lakes Symposium on VLSI 2024: 564-568 - [c46]Tasnuva Farheen, Sourav Roy, Jia Di, Shahin Tajik, Domenic Forte:
Calibratable Polymorphic Temperature Sensor for Detecting Fault Injection and Side-Channel Attacks. HOST 2024: 211-221 - [c45]Trent Reichenbach, Chenglong Fu, Xiaojiang Du, Jia Di, Yuede Ji:
TrustEvent: Cross-Platform IoT Trigger Event Verification Using Edge Computing. ICC 2024: 4084-4089 - [c44]Chenglong Fu, Xiaojiang Du, Qiang Zeng, Zhenyu Zhao, Fei Zuo, Jia Di:
Seeing Is Believing: Extracting Semantic Information from Video for Verifying IoT Events. WISEC 2024: 101-112 - 2023
- [c43]John Swaim, Chad Workman, Jia Di, Xiaojiang Du:
An Internet of Things Testbed for Education and Community Research. AIBThings 2023: 1-5 - [c42]Cole Sherrill, Kyle Orman, Nicholas Brown, Jia Di:
Case Study for Skewing MTNCL Circuits. ASYNC 2023: 20-26 - 2022
- [j22]Baha' A. Alsaify, Dale R. Thompson, Abdallah Y. Alma'aitah, Jia Di:
Using dummy data for RFID tag and reader authentication. Digit. Commun. Networks 8(5): 804-813 (2022) - [j21]Brett Sparkman, Scott C. Smith, Jia Di:
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism. J. Electron. Test. 38(3): 321-334 (2022) - [j20]Chuxiong Wu, Xiaopeng Li, Fei Zuo, Lannan Luo, Xiaojiang Du, Jia Di, Qiang Zeng:
Use It-No Need to Shake It!: Accurate Implicit Authentication for Everyday Objects with Smart Sensing. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 6(3): 146:1-146:25 (2022) - 2021
- [c41]Spencer Nelson, Sang Yun Kim, Jia Di, Zhe Zhou, Zhihang Yuan, Guangyu Sun:
Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks. ASYNC 2021: 48-54 - [c40]Chandler Bernard, William Bryant, Richard Becker, Jia Di:
Design of Asynchronous Polymorphic Logic Gates for Hardware Security. HPEC 2021: 1-5 - [c39]Spencer Nelson, Wassim Khalil, SangYun Kim, Jia Di, Zhe Zhou, Zhihang Yuan, Guang-Yu Sun:
Rapid Configuration of Asynchronous Recurrent Neural Networks for ASIC Implementations. HPEC 2021: 1-6 - [c38]Noah Waller, Hunter Nauman, Derek Taylor, Rafael Del Carmen, Jia Di:
Character Reassignment for Hardware Trojan Detection. MWSCAS 2021: 861-864 - [c37]Rundong Li, Pinghui Wang, Jiongli Zhu, Junzhou Zhao, Jia Di, Xiaofei Yang, Kai Ye:
Building Fast and Compact Sketches for Approximately Multi-Set Multi-Membership Querying. SIGMOD Conference 2021: 1077-1089 - 2020
- [j19]Jingchen Zhu, Guangyu Sun, Xian Zhang, Chao Zhang, Weiqi Zhang, Yun Liang, Tao Wang, Yiran Chen, Jia Di:
Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2279-2292 (2020) - [c36]Affan Abbasi, Marvin W. Suggs, Logan Walz, Asma Mahar, Ayesha Hassan, Robert C. Murphree, Sajib Roy, Trenton L. Roberts, Jia Di, H. Alan Mantooth:
Wireless Sensor Node Platform for In-Plant Stress Monitoring. IEEE SENSORS 2020: 1-4 - [c35]Sreeja Chowdhury, Rabin Yu Acharya, William Boullion, Andrew Felder, Mark Howard, Jia Di, Domenic Forte:
A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates. ITC 2020: 1-10 - [c34]Cole Sherrill, Michael Tennant, Jia Di:
Reducing Power Consumption in Asynchronous MTNCL Circuits through Selective Sleep. MWSCAS 2020: 29-32 - [c33]Brett Sparkman, Scott C. Smith, Jia Di:
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits. VTS 2020: 1-6
2010 – 2019
- 2019
- [c32]Brendan McGeehan, Flora Smith, Thao Le, Hunter Nauman, Jia Di:
Hardware IP Classification through Weighted Characteristics. HPEC 2019: 1-6 - 2018
- [j18]Travis Meade, Kaveh Shamsi, Thao Le, Jia Di, Shaojie Zhang, Yier Jin:
The Old Frontier of Reverse Engineering: Netlist Partitioning. J. Hardw. Syst. Secur. 2(3): 201-213 (2018) - [j17]Yu Bai, Ronald F. DeMara, Jia Di, Mingjie Lin:
Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm. IEEE Trans. Computers 67(5): 631-645 (2018) - [c31]Thao Le, Lucas Weaver, Jia Di, Shaojie Zhang, Yier Jin:
Hardware Trojan Detection and Functionality Determination for Soft IPs. IVSW 2018: 56-61 - [c30]Kelby Haulmark, Wassim Khalil, William Bouillon, Jia Di:
Comprehensive Comparison of NULL Convention Logic Threshold Gate Implementations. NGCAS 2018: 37-40 - 2017
- [j16]Jia Di, Brent A. Bell, William Bouillon, John Brady, Thao Le, Chien-Wei Lo, Liang Men, Spencer Nelson, Francis Sabado, Andrew Suchanek:
Recent Advances in Low Power Asynchronous Circuit Design. J. Low Power Electron. 13(3): 280-297 (2017) - [j15]Sajib Roy, Robert C. Murphree, Affan Abbasi, Ashfaqur Rahman, Shamim Ahmed, James Austin Gattis, Matt Francis, Jim Holmes, H. Alan Mantooth, Jia Di:
A SiC CMOS Digitally Controlled PWM Generator for High-Temperature Applications. IEEE Trans. Ind. Electron. 64(10): 8364-8372 (2017) - [j14]Zimu Guo, Jia Di, Mark M. Tehranipoor, Domenic Forte:
Obfuscation-Based Protection Framework against Printed Circuit Boards Unauthorized Operation and Reverse Engineering. ACM Trans. Design Autom. Electr. Syst. 22(3): 54:1-54:31 (2017) - [c29]Thao Le, Jia Di:
Golden reference matching for gate-level netlist functionality identification. MWSCAS 2017: 567-570 - 2016
- [c28]Xian Zhang, Guangyu Sun, Yaojun Zhang, Yiran Chen, Hai Li, Wujie Wen, Jia Di:
A novel PUF based on cell error rate distribution of STT-RAM. ASP-DAC 2016: 342-347 - [c27]Thao Le, Jia Di, Mark M. Tehranipoor, Domenic Forte, Lei Wang:
Tracking Data Flow at Gate-Level through Structural Checking. ACM Great Lakes Symposium on VLSI 2016: 185-189 - [c26]Jean Pierre T. Habimana, Francis Sabado, Jia Di:
Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation. ISCAS 2016: 750-753 - 2015
- [c25]Zimu Guo, Mark M. Tehranipoor, Domenic Forte, Jia Di:
Investigation of obfuscation-based anti-reverse engineering for printed circuit boards. DAC 2015: 114:1-114:6 - [c24]Shuai Chen, Junlin Chen, Domenic Forte, Jia Di, Mark M. Tehranipoor, Lei Wang:
Chip-level anti-reverse engineering using transformable interconnects. DFTS 2015: 109-114 - [c23]Qinghua Li, Chase Ross, Jing Yang, Jia Di, Juan Carlos Balda, H. Alan Mantooth:
The effects of flooding attacks on time-critical communications in the smart grid. ISGT 2015: 1-5 - [c22]Xian Zhang, Guangyu Sun, Chao Zhang, Weiqi Zhang, Yun Liang, Tao Wang, Yiran Chen, Jia Di:
Fork path: improving efficiency of ORAM by removing redundant memory accesses. MICRO 2015: 102-114 - [c21]Ang Li, Qinghua Li, Vincent C. Hu, Jia Di:
Evaluating the capability and performance of access control policy verification tools. MILCOM 2015: 366-371 - 2014
- [j13]Liang Men, Jia Di:
Asynchronous Parallel Platforms with Balanced Performance and Energy. J. Low Power Electron. 10(4): 566-579 (2014) - [j12]Dale R. Thompson, Jia Di, Michael K. Daugherty:
Teaching RFID Information Systems Security. IEEE Trans. Educ. 57(1): 42-47 (2014) - [c20]Landon Caley, Chien-Wei Lo, Francis Sabado, Jia Di:
A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits. ICICDT 2014: 1-4 - [c19]Liang Men, Brent Hollosi, Jia Di:
Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency. ISVLSI 2014: 7-12 - [c18]Liang Men, Jia Di:
An asynchronous finite impulse response filter design for Digital Signal Processing circuit. MWSCAS 2014: 25-28 - [c17]Liang Men, Jia Di:
Framework of a scalable delay-insensitive asynchronous platform enabling heterogeneous concurrency. MWSCAS 2014: 113-116 - [c16]Baha' A. Alsaify, Dale R. Thompson, Jia Di:
Exploiting hidden Markov models in identifying passive UHF RFID tags. RWS 2014: 259-261 - 2013
- [j11]Michael Hinds, Brett Sparkman, Jia Di, Scott C. Smith:
An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency. J. Low Power Electron. 9(2): 175-188 (2013) - [j10]Washington Cilio, Michael Linder, Chris Porter, Jia Di, Dale R. Thompson, Scott C. Smith:
Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic. Microelectron. J. 44(3): 258-269 (2013) - [c15]Xian Zhang, Chao Zhang, Guangyu Sun, Jia Di, Tao Zhang:
An efficient run-time encryption scheme for non-volatile main memory. CASES 2013: 24:1-24:10 - 2012
- [c14]Debrup Banerjee, Jiang Li, Jia Di, Dale R. Thompson:
Feature selection for RFID tag identification. CHINACOM 2012: 218-221 - 2011
- [j9]Senthilkumar Chinnappa Gounder Periaswamy, Dale R. Thompson, Jia Di:
Fingerprinting RFID Tags. IEEE Trans. Dependable Secur. Comput. 8(6): 938-943 (2011) - [c13]Guoyuan Fu, H. Alan Mantooth, Jia Di:
A new topology for fully differential amplifiers that enhances their tolerance to external disturbances. ASICON 2011: 124-127 - [c12]Guoyuan Fu, H. Alan Mantooth, Jia Di:
A 12-bit CMOS current steering D/A converter with a fully differential voltage output. ISQED 2011: 398-404 - 2010
- [j8]David Coleman, Jia Di:
Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime. J. Low Power Electron. 6(2): 320-324 (2010) - [j7]Scott C. Smith, Waleed K. Al-Assadi, Jia Di:
Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum. IEEE Trans. Educ. 53(3): 349-357 (2010) - [c11]Scott C. Smith, David Roclin, Jia Di:
Delay-Insensitive Cell Matrix. CDES 2010: 67-73
2000 – 2009
- 2009
- [b1]Scott C. Smith, Jia Di:
Designing Asynchronous Circuits using NULL Convention Logic (NCL). Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2009, ISBN 978-3-031-79799-6 - [c10]Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith:
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 3DIC 2009: 1-5 - [c9]Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di:
Delay-Insensitive Ternary Logic. CDES 2009: 3-0 - [c8]Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di:
Glitch-free design for multi-threshold CMOS NCL circuits. ACM Great Lakes Symposium on VLSI 2009: 215-220 - 2008
- [j6]Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, Scott C. Smith:
Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power. J. Low Power Electron. 4(3): 337-348 (2008) - [c7]Senthilkumar Chinnappa Gounder Periaswamy, Dale R. Thompson, Jia Di:
Ownership Transfer of RFID Tags based on Electronic Fingerprint. Security and Management 2008: 64-67 - 2007
- [j5]Jia Di, Parag K. Lala:
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. J. Electron. Test. 23(2-3): 175-192 (2007) - 2006
- [j4]Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara:
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design. Integr. 39(2): 90-112 (2006) - [j3]Jia Di, Jiann-Shiun Yuan:
Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design. J. Low Power Electron. 2(2): 201-216 (2006) - [j2]Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson:
Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55(2): 406-414 (2006) - [c6]Jia Di, Dilip P. Vasudevan:
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. DELTA 2006: 149-156 - 2005
- [j1]Jiann-Shiun Yuan, Jia Di:
Teaching low-power electronic design in electrical and computer engineering. IEEE Trans. Educ. 48(1): 169-182 (2005) - [c5]Jiann-Shiun Yuan, Jia Di:
Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers. CDES 2005: 218-223 - [c4]Jia Di, Parag K. Lala, Dilip P. Vasudevan:
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT 2005: 371-379 - [c3]Jia Di, Fengwei Yang:
D3L - A framework on fighting against non-invasive attacks to integrated circuits for security applications. Circuits, Signals, and Systems 2005: 73-78 - 2003
- [c2]Jia Di, Jiann-Shiun Yuan:
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. ACM Great Lakes Symposium on VLSI 2003: 64-67 - [c1]Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara:
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. ISVLSI 2003: 260-261
Coauthor Index
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last updated on 2024-09-04 01:22 CEST by the dblp team
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