default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDCDES 2009: Las Vegas, Nevada, USA
- Hamid R. Arabnia, Ashu M. G. Solo:
Proceedings of the 2009 International Conference on Computer Design, CDES 2009, July 13-16, 2009, Las Vegas Nevada, USA. CSREA Press 2009, ISBN 1-60132-096-5
Algorithms, Logic, Circuit/Hardware Design, and Tools
- Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di:
Delay-Insensitive Ternary Logic. CDES 2009: 3-0 - Richard F. Hobson:
A 5T Sram Cell with 4 Power Terminals for Read/Write/Standby Assist. CDES 2009: 10-16 - Indira Dugganapally, Waleed Al-Assadi:
Null Conventional Logic (NCL) Implementation of a Bit-Wise Pipeline Dual-Rail (NCL) 2 (to the power of) S Complement Multiplier. CDES 2009: 17-23 - K. S. Vasundara Patel, K. S. Gurumurthy:
Moving From Binary Towards Multi-valued logic. CDES 2009: 24-30 - Jong Wook Kwak, Ju-Hwan Kim:
Performance Evaluation Model of Branch Input Vectors using Neural Network. CDES 2009: 31-37 - Yong-Sung Jeon, Jong Wook Han:
Compact Design of a Combined MixColumn/InvMixColumn Transformation Module for AES. CDES 2009: 38-41 - Hussain Al-Asaad:
Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling. CDES 2009: 42-47 - Chung-Han Chen, Saritha Akavaram, Hira N. Narang, Fan Wu:
Yield and Reliability Enhancement for VLSI Design. CDES 2009: 48-51 - Rohit Sharma, Nitin, Vivek Kumar Sehgal, Amit Kumar, Preity Gupta, Ashish Nandan Lal:
DELSIC: A Delay Simulator for Interconnect Circuits. CDES 2009: 52-56 - Sung-Bin Kim, Se-Jin Ko, Ki-Young Kim, Seok-Yoon Kim:
Reducing the Far-end Crosstalk Using Advanced Guard Trace in PCB Transmission Lines. CDES 2009: 57-59 - Ki-Young Kim, Sung-Bin Kim, Se-Jin Ko, Seok-Yoon Kim:
Analytic Models for Peak Current Computation in General Interconnect Circuits. CDES 2009: 60-62
Power and Energy
- Nagm Mohamed, Nazeih Botros, Mohamad Alweh:
EPIC: An Energy Exploitative Architecture. CDES 2009: 65-69 - Calvin Chiem, Hussain Al-Asaad:
Low Power Methodologies and Challenges for PWM DC-DC Converters. CDES 2009: 70-75 - Yashpal Singh, Vikram Singh Yadav, Tarun Kumar:
PES: Power Efficient Scatternet. CDES 2009: 76-79 - Yil Suk Yang, Jongdae Kim, Tae Moon Roh, Moon Gyu Jang, Woo Hyun Kwon:
Energy-Aware 32bit Parallel Processing Unit with Multi Operation Modes and 2 Step Data Gating Technique for Multimedia Processor. CDES 2009: 80-84 - David Crites, Eric Jordan, Weidong Liao:
A Survey on Power-Aware Computer System Design. CDES 2009: 85-89
Embedded Systems + SoC + High-Performance Systems and Design Issues
- Amir Khwaja:
A Block Based Validation Methodology for Derivative SoC Products. CDES 2009: 93-99 - Seyyed Amir Asghari, Hamid R. Zarandi, Hossein Pedram, Morteza Ansarinia, Mohammad Khademi:
A Fault Injection Attitude based on Background Debug Mode in Embedded Systems. CDES 2009: 100-104 - Amir Khwaja:
DIM: a Post-Silicon Engineering Impact Analysis Method for Derivative SoC Products. CDES 2009: 105-110 - Xiaobo Li, Ming Fu, Xiangdong Cui, Zhou Zhou:
Super-Program Architectures - A New Driving Method for Executing Instructions. CDES 2009: 111-116
Novel Applications + Tools/OS
- Tuo Shi, Jaehwan Lee:
An O(L) Parallel Shortest Path Algorithm. CDES 2009: 119-124 - Vasily G. Moshnyaga, Koji Hashimoto, Shuhei Higashi:
A Hardware System for Tracking Eyes of Computer User. CDES 2009: 125-130 - Gabriela Mogos:
How to Mark an Image from a Quantum Point of View. CDES 2009: 131-133 - Parviz Palangpour, Ganesh K. Venayagamoorthy, Scott C. Smith:
Particle Swarm Optimization: A Hardware Implementation. CDES 2009: 134-139
Performance Evaluation + Simulation, Modeling, and Testing
- Binu P. John, Pradeep S. Nair, Eugene John, Fred W. Hudson:
Performance Measurement of Single, Dual and Quad Core Machines Using SPEC CPU2006. CDES 2009: 143-149 - Daniel P. Playne, Mitchell Johnson, Kenneth A. Hawick:
Benchmarking GPU Devices with N-Body Simulations. CDES 2009: 150-156
Memory, Cache, Storage, Files, Networking + Device Drivers
- Jack Horner:
Some Power-Law Scaling LImits to Computer Memory Architectures. CDES 2009: 159-163 - Jia-Jhe Li, Yuan-Shin Hwang:
Indirect-Mapped Caches: Approximating Set-Associativity with Direct-Mapped Caches. CDES 2009: 164-170 - Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo:
Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. CDES 2009: 171-177 - Shen-Ming Chung, Shun-Chieh Lin, Chun-Yi Li, Hsiao-Hui Lee, Chi-Chun Chen:
Implementation and Analysis of an Efficient TCP/IP Offload Engine. CDES 2009: 178-183 - Antonio Martí Campoy, Francisco Rodríguez-Ballester, Rafael Ors, Juan José Serrano:
Saving Cache Memory Using a Locking Cache in Real-time Systems. CDES 2009: 184-189
Late Papers
- Mohamed Ayari, Taoufik Aguili, Helmi Temimi, Henri Baudrand:
EM-Modeling of Excitation Source in Transverse Wave Approach (TWA) for RF Integrated Circuits Applications. CDES 2009: 193-199 - Mushtaq Ahmad:
The Computing Technology And John Von Neumann's Computer Architecture Giving Way To Optical Computing. CDES 2009: 200-206 - Brett Davis:
CLIW - Clue - Compressed Long Instruction Words. CDES 2009: 207-210 - Jorge Ortiz:
A Reconfigurable Superscalar Processor Architecture for FPGA-based Designs. CDES 2009: 211-217
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-14 21:21 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
