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ORCIDRichard F. Hobson
Person information
- affiliation: Simon Fraser University, Burnaby, BC, Canada
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2010 – 2019
- 2015
[j8]Richard F. Hobson:
A framework for high-speed parallel-prefix adder performance evaluation and comparison. Int. J. Circuit Theory Appl. 43(10): 1474-1490 (2015)- 2013
- [i1]Hooman Jarollahi, Richard F. Hobson:
Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC. CoRR abs/1302.4464 (2013) - 2010
- [c15]Richard F. Hobson:
A Low-Power, Pulsed Domino CMOS 64-bit Adder. CDES 2010: 55-60 - [c14]Hooman Jarollahi, Richard F. Hobson:
Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC. CDES 2010: 169-175
2000 – 2009
- 2009
- [c13]Richard F. Hobson:
A 5T Sram Cell with 4 Power Terminals for Read/Write/Standby Assist. CDES 2009: 10-16 - 2007
- [j7]Richard F. Hobson:
A New Single-Ended SRAM Cell With Write-Assist. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 173-181 (2007) - 2006
- [j6]Richard F. Hobson, Allan R. Dyck, Keith L. Cheung, Bill Ressl:
Signal Processing with Teams of Embedded Workhorse Processors. EURASIP J. Embed. Syst. 2006 (2006) - 2005
- [c12]Richard F. Hobson, Scott Wakelin:
An Area-Efficient High-Speed AES S-Box Method. IWSOC 2005: 376-379 - 2004
- [c11]Richard F. Hobson, Allan R. Dyck, Keith L. Cheung:
SoC Features for a Multi-Processor WCDMA Base-station Modem. IWSOC 2004: 318-321
1990 – 1999
- 1999
- [j5]Richard F. Hobson, P. S. Wong:
A parallel embedded-processor architecture for ATM reassembly. IEEE/ACM Trans. Netw. 7(1): 23-37 (1999) - [c10]Richard F. Hobson, Allan R. Dyck:
A Multiple-Input Single-Phase Clock Flip-Flop Family. Great Lakes Symposium on VLSI 1999: 240-241 - [c9]R. Balakrishnan, Richard F. Hobson:
A Greedy Router with Technology Targetable Output. Great Lakes Symposium on VLSI 1999: 252-255 - [c8]Allan R. Dyck, Scott Evenson, Henry Fu, Richard F. Hobson:
User selectable feature support for an embedded processor. ISCAS (1) 1999: 9-12 - 1998
- [c7]Richard F. Hobson:
Power Reducing Techniques for Clocked CMOS PLAs. Great Lakes Symposium on VLSI 1998: 34-38 - 1995
- [j4]Richard F. Hobson, Michael W. Fraser:
An efficient maximum-redundancy radix-8 SRT division and square-root method. IEEE J. Solid State Circuits 30(1): 29-38 (1995)
1980 – 1989
- 1989
- [j3]Richard F. Hobson:
Refinements to the regenerative carry scheme. IEEE J. Solid State Circuits 24(6): 1759-1762 (1989) - [c6]Richard F. Hobson, J. D. Hoskin, R. W. Spilsbury:
Opportunities for System and User Features in a New APL Interpreter. APL 1989: 190-196 - 1988
- [j2]Severin Gaudet, Richard F. Hobson, Pradeep Chilka, Thomas W. Calvert:
Multiprocessor experiments for high-speed ray tracing. ACM Trans. Graph. 7(3): 151-179 (1988) - 1984
- [j1]Richard F. Hobson:
A Directly Executable Encoding for APL. ACM Trans. Program. Lang. Syst. 6(3): 314-332 (1984) - 1981
- [c5]Richard F. Hobson:
Software sympathetic chip set design. AFIPS National Computer Conference 1981: 3-10 - [c4]Richard F. Hobson:
Structured Machine Design: An Ongoing Experiement. ISCA 1981: 37-56 - [c3]Richard F. Hobson, Patrick Hannon, Jonathan Thornburg:
High-level microprogramming with APL syntax. MICRO 1981: 131-139
1970 – 1979
- 1978
- [c2]Richard F. Hobson:
Computing science hardware laboratories and the LSI revolution. SIGCSE/CSA 1978: 160-170 - 1976
- [c1]I. Ganapathy, Richard F. Hobson:
GPMS, a general purpose memory management system - user's memory - that is. APL 1976: 155-165
Coauthor Index
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