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ORCID8. Great Lakes Symposium on VLSI 1998: Lafayette, LA, USA
- 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA. IEEE Computer Society 1998, ISBN 0-8186-8409-7
Low Power Circuits and Architectures
- Bhanu Kapoor:
Low Power Memory Architectures for Video Applications. 2-6 - Luca Benini, Giovanni De Micheli, Alberto Macii
, Enrico Macii, Massimo Poncino:
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. 8-12 - Amr M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry:
A Low-Power High-Performance Embedded SRAM Macrocell. 13-17 - Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry:
Low-Power Design of Finite Field Multipliers for Wireless Applications. 19-25 - Dusan Suvakovic, C. André T. Salama:
Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems. 26-29 - Seung-Moon Yoo, Seung-Moon Kang:
A Bootstrapped NMOS Charge Recovery Logic. 30-33 - Richard F. Hobson:
Power Reducing Techniques for Clocked CMOS PLAs. 34-38 - Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. 39-44 - Ahmed M. Shams, Magdy A. Bayoumi:
A New Full Adder Cell for Low-Power Applications. 45-
VLSI Circuits
- Victor Varshavsky:
beta-Driven Threshold Elements. 52-58 - José G. Delgado-Frias, Jabulani Nyathi:
A VLSI High-Performance Encoder with Priority Lookahead. 59-64 - Mayukh Bhattacharya, Pinaki Mazumder:
Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. 65-70 - Azman M. Yusof, Lim Chu Aun, S. M. Rezaul Hasan:
600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications. 71-76 - Tim Bakken, John Choma Jr.:
Stability of a Continuous-Time State Variable Filter with OP-AMP and OTA-C Integrators. 77-82 - I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis:
Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. 83-88 - João Navarro Jr., Wilhelmus A. M. Van Noije:
CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. 89-94 - Mohamed Nekili, Yvon Savaria, Guy Bois:
Design of Clock Distribution Networks in Presence of Process Variations. 95-102 - João Navarro Jr., Wilhelmus A. M. Van Noije:
Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology. 103-107 - Pranjal Srivastava, Andrew Pua, Larry Welch:
Issues in the Design of Domino Logic Circuits. 108-112 - Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo, C. Strano:
A Novel 1.5-V Cmos Mixer. 113-117 - Can K. Sandalci, Sayfe Kiaei:
Analysis of Adaptive CMOS Down Conversion Mixers. 118-121 - Hoda S. Abdel-Aty-Zohdy:
Artificial Neural Network Electronic Nose for Volatile Organic Compounds. 122-
VLSI Architectures
- José G. Delgado-Frias, Richard Diaz:
A VLSI Self-Compacting Buffer for DAMQ Communication Switches. 128-133 - Adger E. Harvin III, José G. Delgado-Frias:
A Dictionary Machine Emulation on a VLSI Computing Tree System. 134-139 - Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John:
Modeling and Analysis of The Difference-Bit Cache. 140-145 - Sandeep Agarwal, Fayez El Guibaly:
Modeling of Shift Register-based ATM Switch. 146-151 - Jen-Chien Tuan, Chein-Wei Jen:
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement. 152-156 - Nien-Tsu Wang, Chen-Wei Jeff Shih, Duan Juat Wong-Ho, Nam Ling:
MPEG-2 Video Decoder for DVD. 157-160 - Eric Senn, Bertrand Y. Zavidovique:
A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine. 161-167 - Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi:
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning. 168-
VLSI Arithmetic
- Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid:
Residue to Binary Number Converters for (2n-1, 2n, 2n+1). 174-178 - Inseop Lee, W. Kenneth Jenkins:
The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer. 179-184 - Alexander Skavantzos:
An Efficient Residue to Weighted Converter for a New Residue Number System. 185-191 - Franco Maloberti, Chen Gang:
The Chinese Abacus Method: Can We Use It for Digital Arithmetic? 192-195 - Gwangwoo Choe, Earl E. Swartzlander Jr.:
Merged Arithmetic for Computing Wavelet Transforms. 196-201 - Saeid Sadeghi-Emamchaie, Graham A. Jullien, Vassil S. Dimitrov, William C. Miller:
Digital Arithmetic Using Analog Arrays. 202-207 - James E. Stine, Michael J. Schulte:
A Combined Interval and Floating Point Multiplier. 208-
Testing
- Irith Pomeranz, Sudhakar M. Reddy:
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. 216-221 - Rajesh Raina, Robert F. Molyneaux:
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. 222-229 - Benoit Provost, Edgar Sánchez-Sinencio, Anna Maria Brosa:
A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection. 230-236 - F. S. Bietti, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto:
VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection. 237-242 - Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy:
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. 243-248 - Kaamran Raahemifar, Majid Ahmadi:
A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits. 249-
VLSI Communication Circuits and Systems
- Robert H. Caverly:
Development of a CMOS Cell Library for RF Wireless and Telecommunications Applications. 258-263 - Carlo Samori, Andrea L. Lacaita, Alfio Zanchi, P. Vita:
Design Issues of LC Tuned Oscillators for Integrated Transceivers. 264-269 - Massimo Alioto, Gaetano Palumbo:
Novel Simple Models Of Cml Propagation Delay. 270-274 - John R. Long:
Next-Generation Narrowband RF Front-Ends in Silicon IC Technology. 275-280 - Hassan O. Elwan, Mohammed Ismail:
Low Voltage Low power CMOS AGC circuit for wireless communication. 281-285 - Louis Luh, John Choma Jr., Jeffrey T. Draper:
A Continuous-Time Switched-Current Sigma-Delta Modulator with Reduced Loop Delay. 286-
Algorithms
- Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha:
An Exact Input Encoding Algorithm for BDDs Representing FSMs. 294-300 - Sudhakar Bobba, Ibrahim N. Hajj:
Maximum Current Estimation in Programmable Logic Arrays. 301-306 - Vishwani D. Agrawal, Sharad C. Seth:
Mutually Disjoint Signals and Probability Calculation in Digital Circuits. 307-312 - Travis E. Doom, Jennifer L. White, Anthony S. Wojcik, Gregory H. Chisholm:
Identifying High-Level Components in Combinational Circuits. 313-318 - Anthony D. Johnson:
Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints. 319-324 - Wolfgang Günther, Rolf Drechsler:
Linear Transformations and Exact Minimization of BDDs. 325-330 - Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino:
Timed Supersetting and the Synthesis of Telescopic Units. 331-337 - Sadiq M. Sait, Habib Youssef, Munir M. Zahra:
Tabu Search Based Circuit Optimization. 338-343 - Dirk Stroobandt, Fadi J. Kurdahi:
On the Characterization of Multi-Point Nets in Electronic Designs. 344-
Formal Verification
- Mostafa M. Aref, Khaled M. Elleithy:
HOOVER: Hardware Object-Oriented Verification. 351-355 - Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song:
MDG-based Verification by Retiming and Combinational Transformations. 356-361 - Arun Chandra, Li-C. Wang, Magdy S. Abadir:
Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. 362-367 - Jianping Lu, Sofiène Tahar:
Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS. 368-
Design Methods
- Mark A. Franklin, Prithvi Prabhu:
Performance Optimization of Self-Timed Circuits. 374-379 - Ahmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef:
Stochastic Evolution Algorithm For Technology Mapping. 380-385 - Kaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha:
RCRS: A Framework for Loop Scheduling with Limited Number of Registers. 386-391 - Herwig Van Marck, Jo Depreitere, Dirk Stroobandt, Jan Van Campenhout:
A Quantitative Study of the Benefits of Area-I/O in FPGAs. 392-399 - Dale E. Hocevar, Ching-Yu Hung, Dan Pickens, Sundararajan Sriram:
Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example. 400-
Low Power
- Jim E. Crenshaw, Majid Sarrafzadeh:
Low Power Driven Scheduling and Binding. 406-413 - Muhammad M. Khellah, Mohamed I. Elmasry:
Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. 414-419 - Vamsi Krishna, N. Ranganathan:
A Methodology for High Level Power Estimation and Exploration. 420-425 - S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin:
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. 426-
Database for CAD
- Karen C. Davis, Satish Venkatesan, Lois M. L. Delcambre:
Sharing Electronic Design Data Via Semantic Spaces. 432-439 - Rick Miller:
VHDL-based EDA Tool Implementation with Java. 440-445 - David Hertweck, Mihaela Nica, Sang-Eon Park, Carla N. Purdy:
Standard Data Representations for VLSI Algorithm Development. 446-451 - Teruhisa Hochin, Tatsuo Tsuji:
A Storage Structure for Graph-Oriented Databases Using an Array of Element Types. 452-
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