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ORCIDN. Ranganathan
Nagarajan Ranganathan
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- affiliation: University of South Florida, Tampa, FL, USA
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2010 – 2019
- 2018
[j85]Santosh Aditham
, Nagarajan Ranganathan:
A System Architecture for the Detection of Insider Attacks in Big Data Systems. IEEE Trans. Dependable Secur. Comput. 15(6): 974-987 (2018)- 2017
- [c158]Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori:
LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems. IPDPS Workshops 2017: 1259-1267 - [i5]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits. CoRR abs/1712.02630 (2017) - 2016
- [j84]Wei-Yu Tsai, Xueqing Li, Matthew Jerry, Baihua Xie, Nikhil Shukla, Huichu Liu, Nandhini Chandramoorthy, Matthew Cotter, Arijit Raychowdhury, Donald M. Chiarulli, Steven P. Levitan, Suman Datta, John Sampson, Nagarajan Ranganathan, Vijaykrishnan Narayanan:
Enabling New Computation Paradigms with HyperFET - An Emerging Device. IEEE Trans. Multi Scale Comput. Syst. 2(1): 30-48 (2016) - [c157]Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori:
Memory access pattern based insider threat detection in big data systems. IEEE BigData 2016: 3625-3628 - [i4]Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori:
Call Trace and Memory Access Pattern based Runtime Insider Threat Detection for Big Data Platforms. CoRR abs/1611.07392 (2016) - [i3]Santosh Aditham, Nagarajan Ranganathan:
A Novel Control-flow based Intrusion Detection Technique for Big Data Systems. CoRR abs/1611.07649 (2016) - [i2]Santosh Aditham, Nagarajan Ranganathan:
A System Architecture for the Detection of Insider Attacks in Big Data Systems. CoRR abs/1612.01587 (2016) - 2015
- [j83]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Reversible logic based multiplication computing unit using binary tree data structure. J. Supercomput. 71(7): 2668-2693 (2015) - [j82]Matthew A. Morrison, Nagarajan Ranganathan, Jay Ligatti:
Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1381-1389 (2015) - [c156]Santosh Aditham, Nagarajan Ranganathan:
A novel framework for mitigating insider attacks in big data systems. IEEE BigData 2015: 1876-1885 - [c155]Tony Casagrande, Nagarajan Ranganathan:
GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games. DATE 2015: 677-682 - [c154]Santosh Aditham, Nagarajan Ranganathan:
An energy-aware scheduling heuristic for distributed systems using non-cooperative games. IGSC 2015: 1-6 - 2014
- [j81]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Efficient reversible NOR gates and their mapping in optical computing domain. Microelectron. J. 45(6): 825-834 (2014) - [j80]Matthew Morrison, Nagarajan Ranganathan:
Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 975-988 (2014) - [j79]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. Trans. Comput. Sci. 24: 37-55 (2014) - [c153]Yue Wang, Nagarajan Ranganathan:
A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures. ISVLSI 2014: 430-435 - [c152]Matthew Morrison, Nagarajan Ranganathan:
Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. VLSID 2014: 470-475 - [c151]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. VLSID 2014: 545-550 - [p1]Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal:
Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits. Field-Coupled Nanocomputing 2014: 133-172 - [e1]Marina L. Gavrilova, C. J. Kenneth Tan, Himanshu Thapliyal, Nagarajan Ranganathan:
Transactions on Computational Science XXIV - Special Issue on Reversible Computing. Lecture Notes in Computer Science 8911, Springer 2014, ISBN 978-3-662-45710-8 [contents] - 2013
- [j78]Sandip Kundu, Saraju P. Mohanty, Nagarajan Ranganathan:
Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits. IET Circuits Devices Syst. 7(5): 221-222 (2013) - [j77]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of efficient reversible logic-based binary and BCD adder circuits. ACM J. Emerg. Technol. Comput. Syst. 9(3): 17:1-17:31 (2013) - [j76]Ransford Hyman Jr., Nagarajan Ranganathan, Thomas Bingel, Deanne Tran Vo:
A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 259-269 (2013) - [j75]Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal:
Design of Testable Reversible Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1201-1209 (2013) - [c150]Matthew Morrison, Nagarajan Ranganathan:
A novel optimization method for reversible logic circuit minimization. ISVLSI 2013: 182-187 - [c149]Matthew Lewandowski, Nagarajan Ranganathan, Matthew Morrison:
Behavioral model of integrated qubit gates for quantum reversible logic design. ISVLSI 2013: 194-199 - [c148]Himanshu Thapliyal, Apeksha Bhatt, Nagarajan Ranganathan:
A new CRL gate as super class of Fredkin gate to design reversible quantum circuits. MWSCAS 2013: 1067-1070 - 2012
- [j74]Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.:
Dynamic clock stretching for variation compensation in VLSI circuit design. ACM J. Emerg. Technol. Comput. Syst. 8(3): 16:1-16:13 (2012) - [c147]Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan:
Run-time power-gating in caches of GPUs for leakage energy savings. DATE 2012: 300-303 - [c146]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Mach-Zehnder interferometer based design of all optical reversible binary adder. DATE 2012: 721-726 - [c145]Himanshu Thapliyal, Nagarajan Ranganathan:
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. ISVLSI 2012: 5-6 - [c144]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. ISVLSI 2012: 207-212 - [c143]Matthew Morrison, Nagarajan Ranganathan:
Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles. ISVLSI 2012: 219-224 - [c142]Matthew Morrison, Matthew Lewandowski, Nagarajan Ranganathan:
Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure. ISVLSI 2012: 231-236 - [c141]Himanshu Thapliyal, Nagarajan Ranganathan:
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. VLSI Design 2012: 13-15 - 2011
- [j73]Ransford Hyman Jr., Koustav Bhattacharya, Nagarajan Ranganathan:
Redundancy Mining for Soft Error Detection in Multicore Processors. IEEE Trans. Computers 60(8): 1114-1125 (2011) - [j72]Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori:
State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores. IEEE Trans. Computers 60(11): 1547-1560 (2011) - [j71]Koustav Bhattacharya, N. Ranganathan:
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 918-923 (2011) - [j70]Upavan Gupta, Nagarajan Ranganathan:
A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1723-1726 (2011) - [c140]Yue Wang, N. Ranganathan:
An Instruction-Level Energy Estimation and Optimization Methodology for GPU. CIT 2011: 621-628 - [c139]Himanshu Thapliyal, N. Ranganathan:
A new reversible design of BCD adder. DATE 2011: 1180-1183 - [c138]Matthew Morrison, Nagarajan Ranganathan:
Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. ISVLSI 2011: 126-131 - [i1]Himanshu Thapliyal, Nagarajan Ranganathan:
Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits. CoRR abs/1101.4222 (2011) - 2010
- [j69]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. 6(4): 14:1-14:31 (2010) - [j68]Upavan Gupta, Nagarajan Ranganathan:
A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets. IEEE Trans. Knowl. Data Eng. 22(4): 465-478 (2010) - [j67]Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt:
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 29-38 (2010) - [j66]Venkataraman Mahalingam, N. Ranganathan:
Timing-Based Placement Considering Uncertainty Due to Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 1007-1011 (2010) - [c137]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. VLSI Design 2010: 235-240
2000 – 2009
- 2009
- [j65]Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Variation-aware multimetric optimization during gate sizing. ACM Trans. Design Autom. Electr. Syst. 14(4): 54:1-54:30 (2009) - [j64]Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim:
A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 194-206 (2009) - [j63]Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori:
A Framework for Power-Gating Functional Units in Embedded Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 17(11): 1640-1649 (2009) - [c136]Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori:
Compiler-directed leakage reduction in embedded microprocessors. ICCD 2009: 35-40 - [c135]Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan:
A VLSI System Architecture for Optical Flow Computation. ISCAS 2009: 357-360 - [c134]Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori:
Exploring Compiler Optimizations for Enhancing Power Gating. ISCAS 2009: 1004-1007 - [c133]Himanshu Thapliyal, Nagarajan Ranganathan:
Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. ISCAS 2009: 1815-1818 - [c132]Ransford Hyman Jr., Koustav Bhattacharya, N. Ranganathan:
A Strategy for Soft Error Reduction in Multi Core Designs. ISCAS 2009: 2217-2220 - [c131]Koustav Bhattacharya, Nagarajan Ranganathan:
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. ISQED 2009: 388-393 - [c130]Koustav Bhattacharya, Nagarajan Ranganathan:
A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. ISVLSI 2009: 91-96 - [c129]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. ISVLSI 2009: 229-234 - [c128]Koustav Bhattacharya, Nagarajan Ranganathan:
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. VLSI Design 2009: 453-458 - [c127]Himanshu Thapliyal, Nagarajan Ranganathan:
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design 2009: 511-516 - 2008
- [j62]Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow:
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 975-984 (2008) - [c126]N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. ACM Great Lakes Symposium on VLSI 2008: 171-176 - [c125]Koustav Bhattacharya, Nagarajan Ranganathan:
A linear programming formulation for security-aware gate sizing. ACM Great Lakes Symposium on VLSI 2008: 273-278 - [c124]Upavan Gupta, Nagarajan Ranganathan:
A microeconomic approach to multi-objective spatial clustering. ICPR 2008: 1-4 - [c123]Upavan Gupta, Nagarajan Ranganathan:
An expected-utility based approach to variation aware VLSI optimization under scarce information. ISLPED 2008: 81-86 - [c122]Koustav Bhattacharya, Nagarajan Ranganathan:
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ISLPED 2008: 99-104 - [c121]Venkataraman Mahalingam, Nagarajan Ranganathan:
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI 2008: 329-334 - 2007
- [j61]Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan:
VLSI architecture and chip for combined invisible robust and fragile watermarking. IET Comput. Digit. Tech. 1(5): 600-611 (2007) - [j60]K. P. Subbalakshmi, Rajarathnam Chandramouli, Nagarajan Ranganathan:
A Sequential Distinguisher for Covert Channel Identification. Int. J. Netw. Secur. 5(3): 274-282 (2007) - [j59]Upavan Gupta, Nagarajan Ranganathan:
Multievent Crisis Management Using Noncooperative Multistep Games. IEEE Trans. Computers 56(5): 577-589 (2007) - [c120]Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan:
Improving the reliability of on-chip L2 cache using redundancy. ICCD 2007: 224-229 - [c119]Upavan Gupta, Nagarajan Ranganathan:
A microeconomic approach to multi-robot team formation. IROS 2007: 3019-3024 - [c118]Venkataraman Mahalingam, N. Ranganathan:
Variation Aware Timing Based Placement Using Fuzzy Programming. ISQED 2007: 327-332 - [c117]Narender Hanchate, Nagarajan Ranganathan:
Integrated Gate and Wire Sizing at Post Layout Level. ISVLSI 2007: 225-232 - [c116]Narender Hanchate, Nagarajan Ranganathan:
Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI 2007: 245-252 - [c115]Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan:
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. VLSI Design 2007: 215-220 - 2006
- [j58]Narender Hanchate, Nagarajan Ranganathan:
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. IEEE Trans. Computers 55(8): 1011-1023 (2006) - [j57]Venkataraman Mahalingam, Nagarajan Ranganathan:
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers 55(12): 1523-1535 (2006) - [j56]Saraju P. Mohanty, Nagarajan Ranganathan, Karthikeyan Balakrishnan:
A dual voltage-frequency VLSI chip for image watermarking in DCT domain. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 394-398 (2006) - [j55]Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
ILP models for simultaneous energy and transient power minimization during behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 11(1): 186-212 (2006) - [j54]Narender Hanchate, Nagarajan Ranganathan:
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ACM Trans. Design Autom. Electr. Syst. 11(3): 711-739 (2006) - [j53]Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006) - [c114]Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III:
A novel approach for variation aware power minimization during gate sizing. ISLPED 2006: 174-179 - [c113]Narender Hanchate, Nagarajan Ranganathan:
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ISQED 2006: 92-97 - [c112]Upavan Gupta, N. Ranganathan:
Social Fairness in Multi-Emergency Resource Management. ISTAS 2006: 1-9 - [c111]Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate:
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. ISVLSI 2006: 329-334 - [c110]Narender Hanchate, Nagarajan Ranganathan:
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. VLSI Design 2006: 283-290 - [c109]Venkataraman Mahalingam, N. Ranganathan:
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. VLSI Design 2006: 393-398 - [c108]Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh:
An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. VLSI Design 2006: 477-480 - [c107]Aswath Oruganti, Nagarajan Ranganathan:
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. VLSI Design 2006: 766-769 - 2005
- [j52]Saraju P. Mohanty, N. Ranganathan:
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ACM Trans. Design Autom. Electr. Syst. 10(2): 330-353 (2005) - [j51]Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
A VLSI architecture for watermarking in a secure still digital camera (S2DC) design. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 808-818 (2005) - [j50]Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
A VLSI architecture for visible watermarking in a secure still digital camera (S2/DC) design (Corrected)*. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 1002-1012 (2005) - [c106]Venkataraman Mahalingam, N. Ranganathan:
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ISVLSI 2005: 180-185 - [c105]Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan:
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. VLSI Design 2005: 153-158 - [c104]Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591 - 2004
- [j49]Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan:
Stochastic channel-adaptive rate control for wireless video transmission. Pattern Recognit. Lett. 25(7): 793-806 (2004) - [j48]N. Ranganathan:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 1-11 (2004) - [j47]Narender Hanchate, Nagarajan Ranganathan:
LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 196-205 (2004) - [j46]Saraju P. Mohanty, Nagarajan Ranganathan:
A framework for energy and transient power reduction during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 562-572 (2004) - [j45]Sanjukta Bhanja, N. Ranganathan:
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1360-1370 (2004) - [c103]Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui:
Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI 2004: 187-192 - [c102]Ashok K. Murugavel, N. Ranganathan:
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. VLSI Design 2004: 195-200 - [c101]Narender Hanchate, Nagarajan Ranganathan:
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design 2004: 228-233 - [c100]Ashok K. Murugavel, N. Ranganathan:
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. VLSI Design 2004: 670- - [c99]Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi:
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. VLSI Design 2004: 745-748 - [c98]Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. VLSI Design 2004: 1063- - 2003
- [j44]Abdel Ejnioui, N. Ranganathan:
Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 71-78 (2003) - [j43]Abdel Ejnioui, N. Ranganathan:
Routing on field-programmable switch matrices. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 283-287 (2003) - [j42]Sanjukta Bhanja, N. Ranganathan:
Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 558-567 (2003) - [j41]Ashok K. Murugavel, N. Ranganathan:
Petri net modeling of gate and interconnect delays for power estimation. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 921-927 (2003) - [j40]Ashok K. Murugavel, N. Ranganathan:
A game theoretic approach for power optimization during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1031-1043 (2003) - [c97]N. Ranganathan, Ashok K. Murugavel:
A low power scheduler using game theory. CODES+ISSS 2003: 126-131 - [c96]Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
Simultaneous peak and average power minimization during datapath scheduling for DSP processors. ACM Great Lakes Symposium on VLSI 2003: 215-220 - [c95]N. Ranganathan, Ashok K. Murugavel:
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. ICCD 2003: 276-281 - [c94]Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. ICCD 2003: 441-443 - [c93]Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi:
Transient power minimization through datapath scheduling in multiple supply voltage environment. ICECS 2003: 300-303 - [c92]Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. ISCAS (5) 2003: 313-316 - [c91]Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
Peak Power Minimization Through Datapath Scheduling. ISVLSI 2003: 121-126 - [c90]Saraju P. Mohanty, N. Ranganathan:
Energy Efficient Scheduling for Datapath Synthesis. VLSI Design 2003: 446-451 - [c89]Ashok K. Murugavel, N. Ranganathan:
A Game-Theoretic Approach for Binding in Behavioral Synthesis. VLSI Design 2003: 452- - [c88]Saraju P. Mohanty, N. Ranganathan:
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. VLSI Design 2003: 539-545 - 2002
- [j39]Hitoshi Oi, N. Ranganathan:
A comparative study of bidirectional ring and crossbar interconnection networks. Comput. Electr. Eng. 28(1): 43-57 (2002) - [j38]Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali:
Least-square estimation of average power in digital CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(1): 55-58 (2002) - [c87]K. Sitaraman, N. Ranganathan, Abdel Ejnioui:
A VLSI Architecture for Object Recognition Using Tree Matching. ASAP 2002: 325-334 - [c86]Ashok K. Murugavel, N. Ranganathan:
Petri net modeling of gate and interconnect delays for power estimation. DAC 2002: 455-460 - [c85]Sanjukta Bhanja, N. Ranganathan:
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. ICCD 2002: 388-390 - [c84]Ashok K. Murugavel, N. Ranganathan:
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. ISLPED 2002: 267-270 - [c83]Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna:
Datapath Scheduling using Dynamic Frequency Clocking. ISVLSI 2002: 65-70 - [c82]Ashok K. Murugavel, N. Ranganathan:
A Real Delay Switching Activity Simulator Based on Petri Net Modeling. ASP-DAC/VLSI Design 2002: 181-186 - [c81]Sanjukta Bhanja, N. Ranganathan:
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. ASP-DAC/VLSI Design 2002: 187-192 - 2001
- [j37]Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan:
Context-based lossless image coding using EZW framework. IEEE Trans. Circuits Syst. Video Technol. 11(4): 554-559 (2001) - [j36]N. Ranganathan, Minesh I. Patel, R. Sathyamurthy:
An intelligent system for failure detection and control in an autonomous underwater vehicle. IEEE Trans. Syst. Man Cybern. Part A 31(6): 762-767 (2001) - [j35]Abdel Ejnioui, N. Ranganathan:
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 407-410 (2001) - [j34]Minesh I. Patel, N. Ranganathan:
IDUTC: an intelligent decision-making system for urban traffic-control applications. IEEE Trans. Veh. Technol. 50(3): 816-829 (2001) - [c80]Sanjukta Bhanja, N. Ranganathan:
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. DAC 2001: 209-214 - [c79]Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali:
Average Power in Digital CMOS Circuits using Least Square Estimation. VLSI Design 2001: 215-220 - 2000
- [j33]Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan:
VBR video traffic management using a predictor-based architecture. Comput. Commun. 23(1): 62-70 (2000) - [j32]Hitoshi Oi, N. Ranganathan:
Utilization of cache area in on-chip multiprocessor. Microprocess. Microsystems 24(8): 429-436 (2000) - [c78]Raju D. Venkataramana, N. Ranganathan:
New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. Heterogeneous Computing Workshop 2000: 160-167 - [c77]Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan:
CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. VLSI Design 2000: 228-233 - [c76]Abdel Ejnioui, N. Ranganathan:
Design Partitioning on Single-Chip Emulation Systems. VLSI Design 2000: 234-239 - [c75]Abdel Ejnioui, N. Ranganathan:
Routing on Switch Matrix Multi-FPGA Systems. VLSI Design 2000: 248-253
1990 – 1999
- 1999
- [j31]Ramamurti Chandramouli, N. Ranganathan:
Computing the bivariate Gaussian probability integral. IEEE Signal Process. Lett. 6(6): 129-131 (1999) - [j30]Veeru N. Ramaswamy, N. Ranganathan, Kameswara Rao Namuduri:
Performance analysis of wavelets in embedded zerotree-based lossless image coding schemes. IEEE Trans. Signal Process. 47(3): 884-889 (1999) - [j29]Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan:
Computation of lower bounds for switching activity using decision theory. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 125-129 (1999) - [j28]Vamsi Krishna, N. Ranganathan, Abdel Ejnioui:
A tree-matching chip. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 277-280 (1999) - [c74]Narayanan Vijaykrishnan, N. Ranganathan:
Tuning Branch Predictors to Support Virtual Method Invocation in Java. COOTS 1999: 217-228 - [c73]Abdel Ejnioui, N. Ranganathan:
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. FPGA 1999: 176-185 - [c72]Raju D. Venkataramana, N. Ranganathan:
Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. Heterogeneous Computing Workshop 1999: 137-145 - [c71]Veeraraghavan N. Ramaswamy, Kamesh Namuduri, Nagarajan Ranganathan:
Context modeling of wavelet coefficients in EZW-based lossless image coding. ICASSP 1999: 3165-3168 - [c70]Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan:
Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. ISCAS (4) 1999: 323-326 - [c69]Hitoshi Oi, N. Ranganathan:
Utilization of Cache Area in On-Chip Multiprocessor. ISHPC 1999: 373-380 - [c68]Raju D. Venkataramana, N. Ranganathan:
A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. SAC 1999: 541-547 - [c67]Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan:
Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. VLSI Design 1999: 440- - 1998
- [j27]Girish Chiruvolu, Ravi Sankar, N. Ranganathan:
Adaptive VBR video traffic management for higher utilization of ATM networks. Comput. Commun. Rev. 28(3): 27-40 (1998) - [j26]N. Ranganathan:
A Forum for VLSI Practitioners. Computer 31(10): 86 (1998) - [j25]N. Ranganathan, Raghu Sastry, Raguveer Venkatesan:
SMAC: A VLSI Architecture for Scene Matching. Real Time Imaging 4(3): 171-180 (1998) - [j24]Ramamurti Chandramouli, N. Ranganathan:
A generalized sequential sign detector for binary hypothesis testing. IEEE Signal Process. Lett. 5(11): 295-297 (1998) - [j23]Raghu Sastry, N. Ranganathan:
A VLSI Architecture for Approximate Tree Matching. IEEE Trans. Computers 47(3): 346-352 (1998) - [j22]Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss:
Adaptive quantization and fast error-resilient entropy coding for image transmission. IEEE Trans. Circuits Syst. Video Technol. 8(4): 411-421 (1998) - [j21]Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar:
A linear array processor with dynamic frequency clocking for image processing applications. IEEE Trans. Circuits Syst. Video Technol. 8(4): 435-445 (1998) - [c66]Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss:
Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. Data Compression Conference 1998: 531 - [c65]Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla:
Object-Oriented Architectural Support for a Java Processor. ECOOP 1998: 330-354 - [c64]Vamsi Krishna, N. Ranganathan:
A Methodology for High Level Power Estimation and Exploration. Great Lakes Symposium on VLSI 1998: 420-425 - [c63]Girish Chiruvolu, Tapas K. Das, Ravi Sankar, N. Ranganathan:
A scene-based generalized Markov chain model for VBR video traffic. ICC 1998: 554-558 - [c62]Raju D. Venkataramana, N. Ranganathan:
A simple adaptive wormhole routing algorithm for MIMD systems. ICCD 1998: 205-207 - [c61]Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan:
Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. ICIP (1) 1998: 649-653 - [c60]Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan:
An adaptive scheme for better utilization with QoS constraints for VBR video traffic in ATM networks. ISCC 1998: 3-7 - [c59]Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan:
Rate control for a video coder using learning automata. SMC 1998: 4630-4635 - [c58]Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan:
Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. VLSI Design 1998: 230-233 - [c57]Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu:
A VLSI ATM Switch Architecture for VBR Traffic. VLSI Design 1998: 420-427 - 1997
- [c56]Hitoshi Oi, N. Ranganathan:
Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. ICCD 1997: 267-272 - [c55]Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan:
Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes. ICIP (2) 1997: 278-281 - [c54]Ashley Rasquinha, N. Ranganathan:
C3L: A Chip for Connected Component Labeling. VLSI Design 1997: 446-450 - 1996
- [c53]Minesh I. Patel, N. Ranganathan:
A VLSI System Architecture For Real-Time Intelligent Decision Making. ASAP 1996: 221-230 - [c52]Nagarajan Ranganathan, Rajesh Chandra:
A linear systolic algorithm and architecture for convex bipartite matching. HiPC 1996: 379-384 - [c51]N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar:
A VLSI array architecture with dynamic frequency clocking. ICCD 1996: 137-140 - [c50]S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri:
A VLSI chip for image compression using variable block size segmentation. ICCD 1996: 500-505 - [c49]Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar:
DFLAP: a dynamic frequency linear array processor. ICIP (2) 1996: 1007-1010 - [c48]Minesh I. Patel, N. Ranganathan:
PANTHER: a parallel neuro-systolic architecture for real-time processing. ICNN 1996: 1006-1011 - [c47]S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri:
A VLSI system architecture for lossless image compression. ICPR 1996: 594-598 - [c46]N. Ranganathan, N. Bhavanishankar, Narayanan Vijaykrishnan:
A dynamic frequency linear array processor for image processing. ICPR 1996: 611-615 - [c45]S. Arumugavelu, N. Ranganathan:
SIMD algorithms for single link and complete link pattern clustering. ICPR 1996: 625-629 - [c44]Kameswara Rao Namuduri, N. Ranganathan, Hooman Rashedi:
SVBS: a high-resolution medical image compression algorithm using slicing with variable block size segmentation. ICPR 1996: 919-923 - [c43]Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan:
Lossless image compression using wavelet decomposition. ICPR 1996: 924-928 - [c42]Minesh I. Patel, N. Ranganathan:
An intelligent system architecture for urban traffic control applications. SPDP 1996: 10-17 - [c41]Nina Saxena, Sudeep Sarkar, N. Ranganathan:
Mapping and parallel implementation of Bayesian belief networks. SPDP 1996: 608-611 - [c40]Vamsi Krishna, Abdel Ejnioui, N. Ranganathan:
A tree matching chip. VLSI Design 1996: 280-285 - [c39]Narayanan Vijaykrishnan, N. Ranganathan:
SUBGEN: a genetic approach for subcircuit extraction. VLSI Design 1996: 343-345 - 1995
- [j20]N. Ranganathan, Sharad C. Seth:
Conference Reports. IEEE Des. Test Comput. 12(2): 5, 81 (1995) - [j19]Raghu Sastry, N. Ranganathan:
PMAC: A Polygon Matching Chip. Int. J. Pattern Recognit. Artif. Intell. 9(2): 367-385 (1995) - [j18]Raghu Sastry, N. Ranganathan, Klinton Remedios:
CASM: A VLSI Chip for Approximate String Matching. IEEE Trans. Pattern Anal. Mach. Intell. 17(8): 824-830 (1995) - [j17]Raghu Sastry, N. Ranganathan, Ramesh C. Jain:
VLSI Architectures for High-Speed Range Estimation. IEEE Trans. Pattern Anal. Mach. Intell. 17(9): 894-899 (1995) - [j16]Mario Kovac, N. Ranganathan:
JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard. Proc. IEEE 83(2): 247-258 (1995) - [j15]Nagarajan Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri:
A lossless image compression algorithm using variable block size segmentation. IEEE Trans. Image Process. 4(10): 1396-1406 (1995) - [j14]Nagarajan Ranganathan, Rajiv Mehrotra, S. Subramaniam:
A high speed systolic architecture for labeling connected components in an image. IEEE Trans. Syst. Man Cybern. 25(3): 415-423 (1995) - [c38]Mario Kovac, N. Ranganathan, Martin Zagar:
A prototype VLSI chip architecture for JPEG image compression. ED&TC 1995: 2-6 - [c37]N. Ranganathan, K. B. Doreswamy:
A systolic algorithm and architecture for image thinning. Great Lakes Symposium on VLSI 1995: 138-143 - [c36]Raghu Sastry, N. Ranganathan:
A VLSI Architecture for Computer the Tree-to-Tree Distance. HPCA 1995: 330-339 - [c35]Abdel Ejnioui, N. Ranganathan:
Systolic algorithms for tree pattern matching. ICCD 1995: 650-702 - [c34]Mario Kovac, N. Ranganathan:
JAGUAR: a high speed VLSI chip for JPEG image compression standard. VLSI Design 1995: 220-224 - 1994
- [j13]N. Ranganathan, Raghu Sastry:
VLSI Architectures for Pattern Matching. Int. J. Pattern Recognit. Artif. Intell. 8(4): 815-843 (1994) - [j12]Ken Hughes, N. Ranganathan:
Modeling Sensor Confidence for Sensor Integration Tasks. Int. J. Pattern Recognit. Artif. Intell. 8(6): 1301-1318 (1994) - [j11]Kameswara Rao Namuduri, Rajiv Mehrotra, Nagarajan Ranganathan:
Efficient computation of gabor filter based multiresolution responses. Pattern Recognit. 27(7): 925-938 (1994) - [c33]N. Ranganathan, Satish Venugopal:
A VLSI Chip for Template Matching. ICCD 1994: 542-545 - [c32]N. Ranganathan, Satish Venugopal:
An Efficient VLSI Architecture for Template Matching. ICPP (1) 1994: 224-231 - [c31]N. Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri:
A lossless image compression algorithm using variable block size segmentation. ICPR (3) 1994: 40-44 - [c30]N. Ranganathan, Satish Venugopal:
An efficient VLSI architecture for template matching based on moment preserving pattern matching. ICPR (3) 1994: 388-390 - [c29]N. Ranganathan, Bharadwaj Parthasarathy, Ken Hughes:
A Parallel Algorithm and Architecture for Robot Path Planning. IPPS 1994: 275-279 - [c28]Mario Kovac, N. Ranganathan:
ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. VLSI Design 1994: 291-296 - 1993
- [j10]Mario Kovac, N. Ranganathan, M. Varanasi:
SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. IEEE Trans. Very Large Scale Integr. Syst. 1(1): 22-30 (1993) - [j9]Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya:
MARVLE: a VLSI chip for data compression using tree-based codes. IEEE Trans. Very Large Scale Integr. Syst. 1(2): 203-214 (1993) - [j8]Raghu Sastry, N. Ranganathan, Horst Bunke:
VLSI architectures for polygon recognition. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 398-407 (1993) - [c27]N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer:
SMAC: A Scene Matching Chip. ICCD 1993: 184-187 - [c26]Raghu Sastry, N. Ranganathan:
A Systolic Array for Approximate String Matching. ICCD 1993: 402-405 - [c25]Ken Hughes, N. Ranganathan:
A Model for Determining Sensor Confidence. ICRA (2) 1993: 136-141 - [c24]Raghu Sastry, N. Ranganathan, Ramesh C. Jain:
VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. IPPS 1993: 700-704 - [c23]Mario Kovac, N. Ranganathan, M. Varanasi:
SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. VLSI Design 1993: 25-30 - [c22]Raghu Sastry, N. Ranganathan, Horst Bunke:
Hardware Algorithms for Polygon Matching. VLSI Design 1993: 41-44 - 1992
- [j7]N. Ranganathan, K. R. Balaji, Hassan N. Srinidhi:
A VLSI systolic array processor chip for computing joins in a relational database. Microprocess. Microsystems 16(5): 227-236 (1992) - [j6]Rajiv Mehrotra, Kameswara Rao Namuduri, Nagarajan Ranganathan:
Gabor filter-based edge detection. Pattern Recognit. 25(12): 1479-1494 (1992) - [c21]Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan:
MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. ICCD 1992: 170-173 - [c20]Minesh I. Patel, Patrick McCabe, N. Ranganathan:
SIBA: a VLSI systolic array chip for image processing. ICPR (4) 1992: 15-18 - [c19]V. K. Sundaresan, Sanjay Nichani, N. Ranganathan, Ravi Sankar:
A VLSI hardware accelerator for dynamic time warping. ICPR (4) 1992: 27-30 - [c18]R. Venkatesan, Raghu Sastry, N. Ranganathan:
A VLSI architecture for hierarchical scene matching. ICPR (4) 1992: 214-217 - [c17]Kameswara Rao Namuduri, Rajiv Mehrotra, N. Ranganathan:
Edge detection models based on Gabor filters. ICPR (3) 1992: 729-732 - [c16]Mario Kovac, N. Ranganathan, M. Varanasi:
A Systolic Algorithm and Architecture for Galois Field Arithmetic. IPPS 1992: 283-288 - [c15]Ken Hughes, Alade Tokuta, N. Ranganathan:
trulla : An Algorithm For Path Planning Among Weighted Regions By Localized Propagations. IROS 1992: 469-476 - [c14]N. Ranganathan, Rajiv Mehrotra, S. Kurji:
A CMOS VLSI Chip for Motion Detection. VLSI Design 1992: 209-214 - [c13]N. Ranganathan, Minesh I. Patel, Patrick McCabe:
A Two-dimensional Systolic Array Processor for Image Processing. VLSI Design 1992: 215-220 - 1991
- [j5]N. Ranganathan, Rajiv Mehrotra:
A VLSI architecture for dynamic scene analysis. CVGIP Image Underst. 53(2): 189-197 (1991) - [j4]N. Ranganathan, Sanjay Nichani, Rajiv Mehrotra:
A VLSI architecture for a half-edge-based corner detector. Mach. Vis. Appl. 4(3): 165-181 (1991) - [c12]N. Ranganathan, Rajiv Mehrotra, Kameswara Rao Namuduri:
An architecture to implement multiresolution. ICASSP 1991: 1157-1160 - [c11]Nagarajan Ranganathan, Rajiv Mehrotra, S. Subramaniam:
A high speed systolic architecture for labeling connected components in an image. SPDP 1991: 818-825 - 1990
- [j3]Rajiv Mehrotra, Sanjay Nichani, Nagarajan Ranganathan:
Corner detection. Pattern Recognit. 23(11): 1223-1233 (1990) - [c10]Sanjay Nichani, N. Ranganathan:
SAP: design of a systolic array processor for computation in vision. ICCD 1990: 315-318 - [c9]K. R. Namaduri, Rajiv Mehrotra, N. Ranganathan:
Fast spatiotemporal filters. ICPR (2) 1990: 479-483 - [c8]N. Ranganathan, Rajiv Mehrotra:
A VLSI architecture for difference picture-based dynamic scene analysis. ICPR (2) 1990: 506-508 - [c7]N. Ranganathan, Hassan N. Srinidhi:
Effect of Data Compression Hardware on the Performance of a Relational Database Machine. PARBASE 1990: 144-146 - [c6]Selwyn Henriques, N. Ranganathan:
A parallel architecture for data compression. SPDP 1990: 260-266
1980 – 1989
- 1989
- [j2]Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan:
Enhancing arithmetic and tree-based coding. Inf. Process. Manag. 25(3): 293-305 (1989) - [c5]Amar Mukherjee, N. Ranganathan, Mostafa A. Bassiouni:
Adaptive and pipelined VLSI designs for tree-based codes. ICCD 1989: 369-372 - [c4]Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan:
On Software and Hardware Techniques of Data Engineering. ICDE 1989: 208-215 - [c3]N. Ranganathan, Rajiv Mehrotra:
A VLSI system for difference picture-based motion analysis. TAI 1989: 592-597 - 1988
- [j1]N. Ranganathan, Mubarak Shah:
A VLSI architecture for computing scale space. Comput. Vis. Graph. Image Process. 43(2): 178-204 (1988) - [c2]Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee:
A scheme for data compression in supercomputers. SC 1988: 272-278 - [c1]Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee:
Software and Hardware Enhancement of Arithmetic Coding. SSDBM 1988: 120-132
Coauthor Index
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