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ORCIDVenkataraman Mahalingam
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2010 – 2019
- 2012
[j6]Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.:
Dynamic clock stretching for variation compensation in VLSI circuit design. ACM J. Emerg. Technol. Comput. Syst. 8(3): 16:1-16:13 (2012)- 2010
- [j5]Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt:
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 29-38 (2010) - [j4]Venkataraman Mahalingam, N. Ranganathan:
Timing-Based Placement Considering Uncertainty Due to Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 1007-1011 (2010)
2000 – 2009
- 2009
- [j3]Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Variation-aware multimetric optimization during gate sizing. ACM Trans. Design Autom. Electr. Syst. 14(4): 54:1-54:30 (2009) - [c9]Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan:
A VLSI System Architecture for Optical Flow Computation. ISCAS 2009: 357-360 - 2008
- [j2]Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow:
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 975-984 (2008) - [c8]N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. ACM Great Lakes Symposium on VLSI 2008: 171-176 - [c7]Venkataraman Mahalingam, Nagarajan Ranganathan:
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI 2008: 329-334 - 2007
- [c6]Venkataraman Mahalingam, N. Ranganathan:
Variation Aware Timing Based Placement Using Fuzzy Programming. ISQED 2007: 327-332 - 2006
- [j1]Venkataraman Mahalingam, Nagarajan Ranganathan:
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers 55(12): 1523-1535 (2006) - [c5]Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III:
A novel approach for variation aware power minimization during gate sizing. ISLPED 2006: 174-179 - [c4]Venkataraman Mahalingam, N. Ranganathan:
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. VLSI Design 2006: 393-398 - 2005
- [c3]Venkataraman Mahalingam, N. Ranganathan:
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ISVLSI 2005: 180-185 - 2004
- [c2]N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu:
Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design. DELTA 2004: 333-340 - 2003
- [c1]N. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu:
Analysis of Bit Transition Count for EDAC Encoded FSM. IOLTS 2003: 166
Coauthor Index
aka: Nagarajan Ranganathan
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