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ORCIDACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10
Volume 10, Number 1, January 2005
- Nikil D. Dutt
:
Editorial. 1-2 - Jason Cong, Hui Huang, Xin Yuan:
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. 3-23 - Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai:
Bipartitioning and encoding in low-power pipelined circuits. 24-32 - Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh:
A scheduling algorithm for optimization and early planning in high-level synthesis. 33-57 - Saurabh N. Adya, Igor L. Markov:
Combinatorial techniques for mixed-size placement. 58-90 - Mehrdad Nourani, Mohammad H. Tehranipour:
RL-huffman encoding for test compression and power reduction in scan applications. 91-115 - Gene Eu Jan, Ki-Yin Chang, Su Gao, Ian Parberry:
A 4-geometry maze router and its application on multiterminal nets. 116-135 - Péter Arató, Zoltán Ádám Mann, András Orbán:
Algorithmic aspects of hardware/software partitioning. 136-156 - Dimitrios Kagaris:
A unified method for phase shifter computation. 157-167 - Chi-Chou Kao, Yen-Tai Lai:
An efficient algorithm for finding the minimal-area FPGA technology mapping. 168-186
Volume 10, Number 2, April 2005
- Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria:
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. 187-204 - Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of skewed logic circuits. 205-228 - Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen:
Optimizing instruction TLB energy using software and hardware techniques. 229-257 - Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran:
Efficient techniques for transition testing. 258-278 - Kara K. W. Poon, Steven J. E. Wilton, Andy Yan:
A detailed power model for field-programmable gate arrays. 279-302 - Soumendu Bhattacharya, Abhijit Chatterjee:
Optimized wafer-probe and assembled package test design for analog circuits. 303-329 - Saraju P. Mohanty, N. Ranganathan:
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. 330-353 - Azadeh Davoodi, Ankur Srivastava:
Voltage scheduling under unpredictabilities: a risk management paradigm. 354-368 - Zhong Wang, Xiaobo Sharon Hu:
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures. 369-388 - Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan:
Large-scale circuit placement. 389-430
Volume 10, Number 3, July 2005
- JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy:
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. 431-461 - Arnab Roy, Subrat Kumar Panda, Rajeev Kumar, P. P. Chakrabarti:
A framework for systematic validation and debugging of pipeline simulators. 462-491 - Ansuman Banerjee, Pallab Dasgupta:
The open family of temporal logics: Annotating temporal operators with input constraints. 492-522 - Farinaz Koushanfar, Inki Hong, Miodrag Potkonjak:
Behavioral synthesis techniques for intellectual property protection. 523-545 - Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
Routing-aware scan chain ordering. 546-560 - Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
An algorithm for integrated pin assignment and buffer planning. 561-572 - Jaehwan John Lee, Vincent John Mooney III:
An o(min(m, n)) parallel deadlock detection algorithm. 573-586
Volume 10, Number 4, October 2005
- Ian G. Harris:
Introduction. 587-588 - Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
XFM: An incremental methodology for developing formal models. 589-609 - Masahiro Fujita:
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. 610-626 - Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin:
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator. 627-650 - Jason T. Higgins, Mark D. Aagaard:
Simplifying the design and automating the verification of pipelines with structural hazards. 651-672 - Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
Instruction-level test methodology for CPU core self-testing. 673-689 - Ahmad A. Al-Yamani, Edward J. McCluskey:
Test chip experimental results on high-level structural test. 690-701 - Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen:
An event-based monitoring service for networks on chip. 702-723
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