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Naran Sirisantana
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2000 – 2009
- 2005
- [j4]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005) - 2004
- [j3]Naran Sirisantana, Kaushik Roy:
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. IEEE Des. Test Comput. 21(1): 56-63 (2004) - [j2]Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy:
Enhancing Yield at the End of the Technology Roadmap. IEEE Des. Test Comput. 21(6): 563-571 (2004) - 2003
- [c6]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC 2003: 820-823 - [c5]Naran Sirisantana, Kaushik Roy:
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. DATE 2003: 11160-11161 - [c4]Naran Sirisantana, Kaushik Roy:
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies. ESSCIRC 2003: 181-184 - 2002
- [j1]Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy:
Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 469-476 (2002) - [c3]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234 - 2001
- [c2]Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy:
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270 - 2000
- [c1]Naran Sirisantana, Liqiong Wei, Kaushik Roy:
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. ICCD 2000: 227-232
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