"Synthesis of Selectively Clocked Skewed Logic Circuits."

Aiqun Cao et al. (2002)

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DOI: 10.1109/ISQED.2002.996737

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/isqed/CaoSKR02
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234

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