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ORCIDSaeed Shamshiri
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2010 – 2019
- 2012
[c11]Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani, Shiyuan Yang, Kwang-Ting Cheng
:
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems. ASP-DAC 2012: 615-620- [c10]Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco:
Comprehensive online defect diagnosis in on-chip networks. VTS 2012: 44-49 - 2011
- [j3]Saeed Shamshiri, Kwang-Ting (Tim) Cheng:
Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip. IEEE Trans. Computers 60(9): 1246-1259 (2011) - [c9]Saeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng:
End-to-end error correction and online diagnosis for on-chip networks. ITC 2011: 1-10 - 2010
- [c8]Saeed Shamshiri, Kwang-Ting Cheng:
Error-locality-aware linear coding to correct multi-bit upsets in SRAMs. ITC 2010: 202-211 - [c7]Saeed Shamshiri, Kwang-Ting Cheng:
Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy. VTS 2010: 194-199
2000 – 2009
- 2009
- [c6]Saeed Shamshiri, Kwang-Ting Cheng:
Yield and Cost Analysis of a Reliable NoC. VTS 2009: 173-178 - 2008
- [c5]Saeed Shamshiri, Peter Lisherness, Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng:
A Cost Analysis Framework for Multi-core Systems with Spares. ITC 2008: 1-8 - 2005
- [j2]Saeed Shamshiri, Seid Mehdi Fakhraie:
Genetic-algorithm Memory Minimisation for Designing Reconfigurable Ip Address Lookup Engine. Int. J. Comput. Intell. Appl. 5(1): 69-90 (2005) - [j1]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
Instruction-level test methodology for CPU core self-testing. ACM Trans. Design Autom. Electr. Syst. 10(4): 673-689 (2005) - [c4]Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi:
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Asian Test Symposium 2005: 236-241 - [c3]Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi:
Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) 2005: 424-427 - 2004
- [c2]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. Asian Test Symposium 2004: 158-163 - [c1]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
Instruction level test methodology for CPU core software-based self-testing. HLDVT 2004: 25-29
Coauthor Index
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