default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBijan Alizadeh
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j45]Hamed Hossein-Talaee, Ali Jahanian
, Bijan Alizadeh:
Systematic Trojan Detection in Crypto-Systems Using the Model Checker. J. Circuits Syst. Comput. 33(3) (2024)- [j44]Mohammad Moradi Shahmiri, Bijan Alizadeh:
Concealing Exposed Circuit Features Through a MaxSAT-Based Logic Locking Method. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2039-2043 (2024) - [j43]Ali Falahati, Mahdieh Shamirzaee, Bijan Alizadeh:
An FPGA-Based Hardware Architecture for P + M Class PMU Using Accuracy-Aware O-Spline Filter Selection and Modulation Detection. IEEE Trans. Instrum. Meas. 73: 1-8 (2024) - [j42]Negar Aghapour Sabbagh, Bijan Alizadeh:
Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification. ACM Trans. Design Autom. Electr. Syst. 29(5): 1-19 (2024) - 2023
- [j41]Bijan Alizadeh, Masoud Shiroei:
Automatic correction of RTL designs using a lightweight partial high level synthesis. Integr. 91: 173-181 (2023) - [j40]Abolfazl Sajadi, Ahmad Shabani, Bijan Alizadeh:
DC-PUF: Machine learning-resistant PUF-based authentication protocol using dependency chain for resource-constraint IoT devices. J. Netw. Comput. Appl. 217: 103693 (2023) - 2022
- [j39]Amir Ashtari, Ahmad Shabani, Bijan Alizadeh:
Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices. ISC Int. J. Inf. Secur. 14(3): 1-8 (2022) - [j38]Amir Ashtari, Ahmad Shabani, Bijan Alizadeh:
A comparative study of machine learning classifiers for secure RF-PUF-based authentication in internet of things. Microprocess. Microsystems 93: 104600 (2022) - [j37]Fatemeh Khormizi, Ahmad Shabani, Bijan Alizadeh:
Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2937-2941 (2022) - 2021
- [j36]Ahmad Shabani, Bijan Alizadeh:
Enhancing Hardware Trojan Detection Sensitivity Using Partition-Based Shuffling Scheme. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 266-270 (2021) - [j35]Mohammad Sabri Abrebekoh, Ahmad Shabani, Bijan Alizadeh:
SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2850-2854 (2021) - [c47]Negar Aghapour Sabbagh, Bijan Alizadeh:
Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation. ETS 2021: 1-6 - [i2]Mohammad Hashemi, Bijan Alizadeh:
FPGA-based Implementation of a New Data Frame Correction System for Merging Units. CoRR abs/2108.11886 (2021) - 2020
- [j34]Ahmad Shabani, Bijan Alizadeh:
PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices. J. Netw. Comput. Appl. 167: 102713 (2020) - [j33]Ahmad Shabani, Bijan Alizadeh:
PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 25-33 (2020) - [j32]Siamack BeigMohammadi, Bijan Alizadeh:
Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 272-276 (2020) - [j31]Bijan Alizadeh, Yasaman Abadi:
Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits. IEEE Trans. Circuits Syst. 67-II(12): 3063-3067 (2020) - [j30]Ali Azarmi Gilan, Mohammad Emad, Bijan Alizadeh:
FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 755-759 (2020)
2010 – 2019
- 2019
- [j29]Masoud Shiroei, Bijan Alizadeh, Masahiro Fujita:
Data-path aware high-level ECO synthesis. Integr. 65: 88-96 (2019) - [j28]Bijan Alizadeh, Seyyed Reza Sharafinejad:
Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 245-252 (2019) - [j27]Mojtaba Abbasnezhad, Bijan Alizadeh:
FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors. IEEE Trans. Instrum. Meas. 68(11): 4326-4334 (2019) - [j26]Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh:
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 734-737 (2019) - [c46]Amir Ashtari, Ahmad Shabani, Bijan Alizadeh:
A New RF-PUF Based Authentication of Internet of Things Using Random Forest Classification. ISCISC 2019: 21-26 - 2018
- [j25]Bijan Alizadeh, Mehdi Shakeri:
QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4326-4335 (2018) - [j24]Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi:
Automatic Correction of Dynamic Power Management Architecture in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 308-318 (2018) - [j23]Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1845-1853 (2018) - [c45]Sahand Salamat, Mohammad Reza Azarbad, Bijan Alizadeh:
High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization. ICRC 2018: 1-10 - 2017
- [j22]Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh:
Improved Range Analysis in Fixed-Point Polynomial Data-Path. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1925-1929 (2017) - [j21]Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh:
A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(1): 100-110 (2017) - [j20]Alireza Mahzoon, Bijan Alizadeh:
Systematic Design Space Exploration of Floating-Point Expressions on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 274-278 (2017) - [j19]Shayan Moini, Bijan Alizadeh, Mohammad Emad, Reza Ebrahimpour:
A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications. IEEE Trans. Circuits Syst. II Express Briefs 64-II(10): 1217-1221 (2017) - [j18]Mohammad Reza Azarbad, Bijan Alizadeh:
Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis. ACM Trans. Design Autom. Electr. Syst. 22(2): 22:1-22:22 (2017) - [j17]Alireza Mahzoon, Bijan Alizadeh:
OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 198-209 (2017) - [j16]Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2059-2070 (2017) - [c44]Sahand Salamat, Mehrnaz Ahmadi, Bijan Alizadeh, Masahiro Fujita:
Systematic approximate logic optimization using don't care conditions. ISQED 2017: 419-425 - [c43]Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi:
Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. ISVLSI 2017: 545-550 - [i1]Payman Behnam, Bijan Alizadeh, Sajjad Taheri:
Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs. CoRR abs/1712.09818 (2017) - 2016
- [j15]Mohammad Hashem Haghbayan, Bijan Alizadeh:
A dynamic specification to automatically debug and correct various divider circuits. Integr. 53: 100-114 (2016) - [j14]Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh:
UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 994-998 (2016) - [j13]Hossein Mehri, Bijan Alizadeh:
Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models. ACM Trans. Design Autom. Electr. Syst. 22(1): 13:1-13:17 (2016) - [c42]Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita:
Formally analyzing fault tolerance in datapath designs using equivalence checking. ASP-DAC 2016: 133-138 - [c41]Siamack BeigMohammadi, Bijan Alizadeh:
Combinational trace signal selection with improved state restoration for post-silicon debug. DATE 2016: 1369-1374 - 2015
- [j12]Farimah Farahmandi, Bijan Alizadeh:
Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction. Microprocess. Microsystems 39(2): 83-96 (2015) - [j11]Hossein Mehri, Bijan Alizadeh:
Analytical performance model for FPGA-based reconfigurable computing. Microprocess. Microsystems 39(8): 796-806 (2015) - [j10]Bijan Alizadeh, Payman Behnam, Somayeh Sadeghi Kohan:
A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Trans. Computers 64(6): 1564-1578 (2015) - [j9]Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers 64(6): 1579-1593 (2015) - [j8]Mehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha:
Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2724-2727 (2015) - [c40]Payman Behnam, Bijan Alizadeh:
In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms. ATS 2015: 199-204 - [c39]Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi:
Low power scheduling in high-level synthesis using dual-Vth library. ISQED 2015: 507-511 - [c38]Alireza Mahzoon, Bijan Alizadeh:
Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. ISVLSI 2015: 243-248 - [c37]Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh:
A Timing Error Mitigation Technique for High Performance Designs. ISVLSI 2015: 428-433 - [c36]Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Signature oriented model pruning to facilitate multi-threaded processors debugging. VTS 2015: 1-6 - [c35]Reza Sharafinejad, Bijan Alizadeh, Masahiro Fujita:
UPF-based formal verification of low power techniques in modern processors. VTS 2015: 1-6 - 2014
- [c34]Mehrzad Nejat, Bijan Alizadeh, Ali Afzali-Kusha:
Dynamic Flip-Flop conversion to tolerate process variation in low power circuits. DATE 2014: 1-4 - [c33]Mohammad Hashem Haghbayan, Bijan Alizadeh, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen:
Automated formal approach for debugging dividers using dynamic specification. DFT 2014: 264-269 - [c32]Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi:
Automatic correction of certain design errors using mutation technique. ETS 2014: 1-2 - [c31]Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
Improving polynomial datapath debugging with HEDs. ETS 2014: 1-6 - [c30]Ehsan Qasemi, Amir Samadi, Mohammad H. Shadmehr, Bardia Azizian, Sajjad Mozaffari, Amir Shirian, Bijan Alizadeh:
Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA. FPT 2014: 370-373 - [c29]Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
RTL datapath optimization using system-level transformations. ISQED 2014: 309-316 - [c28]Vahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh:
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression. ISVLSI 2014: 220-225 - [c27]Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi:
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. ISVLSI 2014: 338-343 - [c26]M. H. Haghbayan, Bijan Alizadeh, Payman Behnam, Saeed Safari:
Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism. VLSID 2014: 80-85 - 2013
- [j7]Mohammad Mirzaei, Mahmoud Tabandeh, Bijan Alizadeh, Zainalabedin Navabi:
A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. IEEE Des. Test 30(4): 49-59 (2013) - [j6]Bijan Alizadeh, Payman Behnam:
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs. Microprocess. Microsystems 37(8-D): 1108-1121 (2013) - [c25]Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi:
A probabilistic approach for counterexample generation to aid design debugging. EWDTS 2013: 1-5 - 2012
- [j5]Bijan Alizadeh:
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors. ACM Trans. Design Autom. Electr. Syst. 17(4): 37:1-37:8 (2012) - [c24]Bijan Alizadeh:
A formal approach to debug polynomial datapath designs. ASP-DAC 2012: 683-688 - [c23]Bijan Alizadeh, Masahiro Fujita:
A functional test generation technique for RTL datapaths. HLDVT 2012: 64-70 - [c22]Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita:
Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques. MEMOCODE 2012: 65-74 - 2011
- [c21]Bijan Alizadeh, Masahiro Fujita:
Modular equivalence verification of polynomial datapaths with multiple word-length operands. HLDVT 2011: 9-16 - [c20]Bijan Alizadeh, Masahiro Fujita:
Early case splitting and false path detection to improve high level ATPG techniques. ISCAS 2011: 1463-1466 - [c19]Bijan Alizadeh, Masahiro Fujita:
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. ISQED 2011: 297-302 - 2010
- [j4]Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita:
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 737-748 (2010) - [j3]Bijan Alizadeh, Masahiro Fujita:
Modular Datapath Optimization and Verification Based on Modular-HED. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1422-1435 (2010) - [c18]Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita:
Pipelined Microprocessors Optimization and Debugging. ARC 2010: 435-444 - [c17]Bijan Alizadeh, Masahiro Fujita:
Guided gate-level ATPG for sequential circuits using a high-level test generation approach. ASP-DAC 2010: 425-430 - [c16]Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita:
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). FPGA 2010: 288 - [c15]Bijan Alizadeh, Masahiro Fujita:
A debugging method for repairing post-silicon bugs of high performance processors in the fields. FPT 2010: 328-331 - [c14]Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler:
Polynomial datapath optimization using constraint solving and formal modelling. ICCAD 2010: 756-761
2000 – 2009
- 2009
- [j2]Bijan Alizadeh, Masahiro Fujita:
A Unified Framework for Equivalence Verification of Datapath Oriented Applications. IEICE Trans. Inf. Syst. 92-D(5): 985-994 (2009) - [j1]Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita:
A Formal Approach for Debugging Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 742-754 (2009) - [c13]Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita:
Polynomial datapath optimization using partitioning and compensation heuristics. DAC 2009: 931-936 - [c12]Bijan Alizadeh, Masahiro Fujita:
Modular arithmetic decision procedure with auto-correction mechanism. HLDVT 2009: 138-145 - [c11]Bijan Alizadeh, Masahiro Fujita:
Improved heuristics for finite word-length polynomial datapath optimization. ICCAD 2009: 739-744 - [c10]Omid Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita:
High-level optimization of integer multipliers over a finite bit-width with verification capabilities. MEMOCODE 2009: 56-65 - 2008
- [c9]Bijan Alizadeh, Masahiro Fujita:
Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram. CSICC 2008: 697-704 - [c8]Omid Sarbishei, Bijan Alizadeh, Masahiro Fujita:
Arithmetic Circuits Verification without Looking for Internal Equivalences. MEMOCODE 2008: 7-16 - 2007
- [c7]Bijan Alizadeh, Masahiro Fujita:
Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. ATVA 2007: 129-144 - [c6]Bijan Alizadeh, Masahiro Fujita:
A novel formal approach to generate high-level test vectors without ILP and SAT solvers. HLDVT 2007: 97-104 - 2006
- [c5]Bijan Alizadeh:
Word level functional coverage computation. ASP-DAC 2006: 7-12 - 2005
- [c4]Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi:
Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) 2005: 424-427 - 2004
- [c3]Bijan Alizadeh, Zainalabedin Navabi:
Property Checking based on Hierarchical Integer Equations. ACSD 2004: 26-35 - [c2]Bijan Alizadeh, Zainalabedin Navabi:
Using Integer Equations to Check PSL Properties in RT Level Design. IWSOC 2004: 83-86 - 2003
- [c1]Bijan Alizadeh, Mohammad Reza Kakoee:
Using Integer Equations for High Level Formal Verification Property Checking. ISQED 2003: 69-74
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-04 21:09 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
